Very High Level Synthesis for image processing applications

Bi, Yanjing; Li, Chao; Yang, Fan

doi:10.1145/2967413.2967414

Cited by 4 publications

(3 citation statements)

References 5 publications

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“…Table 6 compares between our tool ViPar and other tools in the literature that are used for high-level exploration for video processing applications. In very highlevel synthesis tool (VHLS) [37], algorithms are described in Matlab or OpenCL. e synthesis of Matlab-to-RTL is explored to change the vector-oriented source code into the scalar-oriented program.…”

Section: Design Space Exploration All Design Variations Listed Inmentioning

confidence: 99%

ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures

Ali

Atitallah

Cadi

et al. 2019

International Journal of Reconfigurable Computing

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Embedded video applications are now involved in sophisticated transportation systems like autonomous vehicles and driver assistance systems. As silicon capacity increases, the design productivity gap grows up for the current available design tools. Hence, high-level synthesis (HLS) tools emerged in order to reduce that gap by shifting the design efforts to higher abstraction levels. In this paper, we present ViPar as a tool for exploring different video processing architectures at higher design level. First, we proposed a parametrizable parallel architectural model dedicated for video applications. Second, targeting this architectural model, we developed ViPar tool with two main features: (1) An empirical model was introduced to estimate the power consumption based on hardware utilization and operating frequency. In addition to that, we derived the equations for estimating the hardware utilization and execution time for each design point during the space exploration process. (2) By defining the main characteristics of the parallel video architecture like parallelism level, the number of input/output ports, the pixel distribution pattern, and so on, ViPar tool can automatically generate the dedicated architecture for hardware implementation. In the experimental validation, we used ViPar tool to generate automatically an efficient hardware implementation for a Multiwindow Sum of Absolute Difference stereo matching algorithm on Xilinx Zynq ZC706 board. We succeeded to increase the design productivity by converging rapidly to the appropriate designs that fit with our system constraints in terms of power consumption, hardware utilization, and frame execution time.

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Section: Design Space Exploration All Design Variations Listed Inmentioning

confidence: 99%

ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures

Ali

Atitallah

Cadi

et al. 2019

International Journal of Reconfigurable Computing

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“…The work of E. Manor [42] demonstrates that this method is an important and effective solution for fast embedded prototyping with efficient performance. This work uses a recently-proposed very high-level synthesis (VHLS) based SW/HW co-design flow [43,44] to facilitate the implementing process from Matlab to RTL. Moreover, different interface and parallel optimizations are made to accelerate the implementations.…”

Section: Introductionmentioning

confidence: 99%

A RTL Implementation of Heterogeneous Machine Learning Network for French Computer Assisted Pronunciation Training

Benezeth

et al. 2023

Applied Sciences

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Computer-assisted pronunciation training (CAPT) is a helpful method for self-directed or long-distance foreign language learning. It greatly benefits from the progress, and of acoustic signal processing and artificial intelligence techniques. However, in real-life applications, embedded solutions are usually desired. This paper conceives a register-transfer level (RTL) core to facilitate the pronunciation diagnostic tasks by suppressing the mulitcollinearity of the speech waveforms. A recently proposed heterogeneous machine learning framework is selected as the French phoneme pronunciation diagnostic algorithm. This RTL core is implemented and optimized within a very-high-level synthesis method for fast prototyping. An original French phoneme data set containing 4830 samples is used for the evaluation experiments. The experiment results demonstrate that the proposed implementation reduces the diagnostic error rate by 0.79–1.33% compared to the state-of-the-art and achieves a speedup of 10.89× relative to its CPU implementation at the same abstract level of programming languages.

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“…The latter approach, however, heavily taxes the limited FPGA memory resources. On the other hand, there is an increasing trend of describing the circuit behaviour using high‐level synthesis tools [7, 8] to reduce the development time and spend more effort at the algorithmic design level. Hardwar Description Language (HDL) Coder and Vision HDL toolboxes in Simulink® by Mathworks® [9, 10] are the examples of commonly employed tools that provide higher level abstraction of image processing and computer vision systems for quick deployment on a variety of target hardware.…”

Section: Introductionmentioning

confidence: 99%

Resource‐efficient FPGA implementation of perspective transformation for bird's eye view generation using high‐level synthesis framework

Bilal

2019

IET Circuits, Devices & Systems

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Bird's eye view (BEV) generation from front-looking video stream is considered an important pre-processing task in various computer vision applications such as driver assistance systems. In this work, hardware implementation of this process using high-level synthesis in Simulink environment has been considered for rapid prototyping under real-time constraints. Traditionally, researchers have employed lookup table-based approaches to circumvent the exorbitant cost of implementing arithmetic modules associated with the perspective transformation. The hardware implementation scheme proposed here, however, demonstrates that a polynomial approximation over the limited domain of the involved operands not only saves precious hardware resources but also provides better fixed-point precision. Synthesis results on Zynq-7000 FPGA show that the proposed circuit reduces the block memory utilisation by 9% compared to the lookup table-based built-in Simulink Vision HDL block. The proposed design evaluates the results in fixed-point format which is essential for subsequent bilinear interpolation to produce high-fidelity output frame, albeit at the cost of 4% increase in DSP48E utilisation. The approximation error of the proposed solution is less than quarter-pixel on average. The proposed hardware has been integrated as an IP core in a hardware-software co-design system. The whole framework is publicly available to facilitate practitioners and researchers.

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Very High Level Synthesis for image processing applications

Cited by 4 publications

References 5 publications

ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures

ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures

A RTL Implementation of Heterogeneous Machine Learning Network for French Computer Assisted Pronunciation Training

Resource‐efficient FPGA implementation of perspective transformation for bird's eye view generation using high‐level synthesis framework

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