Very high voltage planar devices using field plate and semi-resistive layers: design and fabrication

Dragomirescu, Daniela; Charitat, G.; Rossel, F.; Scheid, E.

doi:10.1109/smicnd.2000.890255

Cited by 4 publications

(4 citation statements)

References 6 publications

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“…There are several works on the interaction of termination and passivation structures of high-power silicon devices published, see, for example Refs. [26][27][28][29]. Macary et al have modeled the avalanche breakdown for biased ring structures and floating rings [26].…”

Section: Combined Concepts For Termination and Passivationmentioning

confidence: 99%

“…They show an improvement of the breakdown voltage for the devices with additional SIPOS and additionally conclude a lower sensitivity of the JTE towards implantation dose. In evolution of these works, Dragomirescu et al have combined SIPOS with a Field Plate to fabricate devices with a breakdown voltage up to 4200V and a reduced chip area [29].…”

Section: Combined Concepts For Termination and Passivationmentioning

confidence: 99%

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Passivation in High-Power Si Devices - An Overview

2013

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Passivation of semiconductor devices reaches back to the 1950s with passivation of silicon surfaces by thermally grown oxides. Over the years, the concept has changed towards a detailed balance of breakdown field and leakage current capabilities, involving also the underlying termination areas. In this contribution, a brief historical overview of passivation of Si devices will be given. Based on the underlying physics and lessons learned, an outlook to the challenges for power devices from wide band gap materials, such as silicon carbide, is provided.

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Section: Combined Concepts For Termination and Passivationmentioning

confidence: 99%

Section: Combined Concepts For Termination and Passivationmentioning

confidence: 99%

Passivation in High-Power Si Devices - An Overview

2013

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“…The model analysis indicates that the key factor for reducing the surface electric field is the coupling of the surface potentials with the SIPOS and the underlying silicon, thus leading to increased breakdown voltage [13]- [18]. The structure also extends the depletion region of the main junction such that the potential between the electrodes of two terminals is distributed linearly instead of nonlinearly [19], [20].…”

Section: Introductionmentioning

confidence: 99%

Design, Simulation, and Fabrication of Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) With New Termination Structure

Lin

Wen

2012

IEEE Trans. Electron Devices

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In this paper, we introduce a new type of termination structure utilizing semi-insulating polycrystalline silicon (SIPOS) structures in conjunction with P − junction extension in order to reduce the area of termination device structure and increase the breakdown voltage. In SIPOS structures, one high-resistance layer is deposited between electrodes on two terminals such that the voltage between two electrodes is linearly distributed instead of the original nonlinear distribution. Compared to a traditional termination structure device (with a length of 180 μm and a breakdown voltage at 570 V), the optimal design of the new type of termination structure will lead to an increase of 40 V in the breakdown voltage and a 22.2% area reduction. From the perspective of device fabrication, it has been proven that the new type of termination structure indeed consumes less area while simultaneously realizing an enhanced device breakdown voltage as high as 710 V and a specific on-resistance at 137 mΩ · cm 2 , which is consistent to the simulation results.

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“…Charitat and co-workers published several works on the interaction of termination and passivation structures of high-power silicon devices, see, for example Refs. [12][13][14]. In conclusion of their works, termination and passivation areas cannot be strictly separated any longer, leading to complex three-dimensional structures for termination and passivation areas of high-power silicon devices.…”

mentioning

confidence: 99%