Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories

Семенов, В.К.; Polyakov, Yu. A.; Tolpygo, Sergey K.

doi:10.1109/tasc.2019.2904971

Cited by 47 publications

(48 citation statements)

References 48 publications

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“…Starting from j c = 0.5 mA/μm 2 the junction becomes self-shunted [15,16]. For example, the most functionally dense RAM circuit fabricated recently [17] was based on the Josephson junctions having j c = 0.6 mA/μm 2 with no shunt resistors [16], while minimum junction area was about a ≈ 0.2 μm 2 (β c ≈ 2). However, the criticalcurrent-density increase corresponds to the decrease of tunneling barrier thickness and according increase of its inhomogeneity in coordinate and momentum space.…”

Section: Scalability Of Josephson Junctionsmentioning

confidence: 99%

Miniaturization of Josephson Junctions for Digital Superconducting Circuits

et al. 2021

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In this work, we briefly overview various options for Josephson junctions, which should be scalable down to nanometer range for utilization in nanoscale digital superconducting technology. Such junctions should possess high values of critical current, I c , and normal state resistance, R N . Another requirement is the high reproducibility of the junction parameters across a wafer in a fabrication process. We argue that superconductor-normal metal-superconductor (SN -N -NS) Josephson junction of "variable thickness bridge" geometry is a promising choice to meet these requirements. Theoretical analysis of the SN -N -NS junction is performed in the case where the distance between the S electrodes is comparable to the coherence length of the N material. The restriction on the junction geometrical parameters providing the existence of superconductivity in the S electrodes is derived for the current flowing through the junction of an order of I c . The junction heating, as well as available mechanisms for the heat removal, is analyzed. The obtained results show that a SN -N -NS junction with a high (submillivolt) value of I c R N product can be fabricated from a broadly utilized combination of materials like Nb/Cu using well-established technological processes. The junction area can be scaled down to that of semiconductor transistors fabricated in the frame of a 40-nm process.

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Section: Scalability Of Josephson Junctionsmentioning

confidence: 99%

Miniaturization of Josephson Junctions for Digital Superconducting Circuits

et al. 2021

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“…7,8 However, the lack of a compatible high-density, high-speed memory has been a long-standing bottleneck. 1,9,10 Current SFQ cache memories are mainly composed of volatile shift-register units. 11,12 The storage element area is approximately 60×60 μm 2 .…”

mentioning

confidence: 99%

Miniaturization of the Superconducting Memory Cell via a Three-Dimensional Nb Nano-superconducting Quantum Interference Device

Chen

Wang

et al. 2020

ACS Nano

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Scalable memories that can match the speeds of superconducting logic circuits have long been desired to enable a superconducting computer. A superconducting loop that includes a Josephson junction can store a flux quantum state in picoseconds. However, the requirement for the loop inductance to create a bi-state hysteresis sets a limit on the minimal area occupied by a single memory cell. Here, we present a miniaturized superconducting memory cell based on a Three-Dimensional (3D) Nb nano-Superconducting QUantum Interference Device (nano-SQUID). The major cell area here fits within an 8×9 μm 2 rectangle with a cross-selected function for memory implementation. The cell shows periodic tunable hysteresis between two neighbouring flux quantum states produced by bias current sweeping because of the large modulation depth of the 3D nano-SQUID (~66%). Furthermore, the measured Current-Phase Relations (CPRs) of nano-SQUIDs are shown to be skewed from a sine function, as predicted by theoretical modelling. The skewness and the critical current of 3D nano-SQUIDs are linearly correlated. It is also found that the hysteresis loop size is in a linear scaling relationship with the CPR skewness using the statistics from characterisation of 26 devices. We show that the CPR skewness range of π/4-3π/4 is equivalent to a large loop inductance in creating a stable bi-state hysteresis for memory implementation. Therefore, the skewed CPR of 3D nano-SQUID enables further superconducting memory cell miniaturization by overcoming the inductance limitation of the loop area.

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“…Characterizations of stand-alone SHE-MTJ devices (shown in Fig. 2) were done using the same HPD cryostat and control electronics as described in our previous report 13 . Measurements and data collection procedures were performed using our custombuilt Python package, Auspex, available online at https://github.com/BBN-Q/Auspex.…”

Section: Measurementsmentioning

confidence: 99%

“…CMOS-based memories [8][9][10] provide better scalability but also suffer from their high dynamic power consumption at cryogenic temperatures, in the range of 10-100 pJ/bit. Although there is an active pursuit of other types of superconducting memories [11][12][13][14] , a great deal of effort has been invested in magnetic [15][16][17] and magnetic-superconducting hybrid memories 18,19 which have the potential to offer high speed, low power, nonvolatility, and scalability. Early achievements in cryogenic spin-valves 15,16 and magnetic tunnel junctions 17 (MTJs) have recently been reported with energy consumption per switching of a few tens of fJ.…”

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confidence: 99%

Cryogenic Memory Architecture Integrating Spin Hall Effect based Magnetic Memory and Superconductive Cryotron Devices

Nguyen

Ribeill

Gustafsson

et al. 2020

Sci Rep

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One of the most challenging obstacles to realizing exascale computing is minimizing the energy consumption of L2 cache, main memory, and interconnects to that memory. For promising cryogenic computing schemes utilizing Josephson junction superconducting logic, this obstacle is exacerbated by the cryogenic system requirements that expose the technology's lack of high-density, high-speed and power-efficient memory. Here we demonstrate an array of cryogenic memory cells consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, combined with a superconducting heater-cryotron bit-select element. The write energy of these memory elements is roughly 8 pJ with a bit-select element, designed to achieve a minimum overhead power consumption of about 30%. Individual magnetic memory cells measured at 4 K show reliable switching with write error rates below 10 -6 , and a 4x4 array can be fully addressed with bit select error rates of 10 -6 . This demonstration is a first step towards a full cryogenic memory architecture targeting energy and performance specifications appropriate for applications in superconducting high performance and quantum computing control systems, which require significant memory resources operating at 4 K.An issue with the SHE-MTJ, however, is that its characteristic impedance and switching currents are too large to be directly compatible with our separately fabricated SFQ control circuits. For example, a 300 nm wide, 5 nm thick spin Hall channel requires a switching current of roughly 1 mA into a 0.5 kΩ load, which is incompatible with typical SFQ circuit output impedance of a few Ohms.

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Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories

Cited by 47 publications

References 48 publications

Miniaturization of Josephson Junctions for Digital Superconducting Circuits

Miniaturization of Josephson Junctions for Digital Superconducting Circuits

Miniaturization of the Superconducting Memory Cell via a Three-Dimensional Nb Nano-superconducting Quantum Interference Device

Cryogenic Memory Architecture Integrating Spin Hall Effect based Magnetic Memory and Superconductive Cryotron Devices

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