2016
DOI: 10.1007/s10470-016-0754-9
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Very linear open-loop CMOS sample-and-hold structure for high precision and high speed ADCs

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Cited by 5 publications
(5 citation statements)
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“…Some techniques have been developed by many researchers to decrease hold error voltage in S/H circuit [12][13][14][15][16][17][18][19][20][21]. Most of them use an additional circuit to decrease the hold error.…”
Section: Proposed Methodsmentioning
confidence: 99%
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“…Some techniques have been developed by many researchers to decrease hold error voltage in S/H circuit [12][13][14][15][16][17][18][19][20][21]. Most of them use an additional circuit to decrease the hold error.…”
Section: Proposed Methodsmentioning
confidence: 99%
“…From equation 13it can be known that total hold error consists of two simple parts with a different sign, the width of P-type MOS transistor W P with a coefficient a and width of N-type MOS transistor W N with a coefficient -b. The coefficient a and b is shown in equations (14) and (15), respectively. These equations can now be used to adjust W P and W N properly to achieve zero hold error.…”
Section: Proposed Methodsmentioning
confidence: 99%
“…The other technique is bottom plate sampling. Recently, the improvement of bottom plate sampling is reported in [8,9]. This technique shows decent performance to decrease charge injection and clock feedthrough effect, but the complex clocking phase in this technique rises another problem in system complexity.…”
Section: Channel Charge Injection Clock Feedthrough and On-resistancmentioning
confidence: 99%
“…Based on the operation principles explanation, the output of NMOS and PMOS bootstrap circuits can be written in Eqs. (8) and 9, respectively.…”
Section: Proposed S/h Circuitmentioning
confidence: 99%
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