Very low resource table-based FPGA evaluation of elementary functions

Neto, Horácio C.; Véstias, Mário P.

doi:10.1109/reconfig.2013.6732336

Cited by 10 publications

(7 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus, x 0 has to be determined before computing the iteration equation. The usual method involves scaling the input a in a predetermined interval as [7]. Then, x 0 can be calculated by using coefficients stored in a memory block.…”

Section: Related Workmentioning

confidence: 99%

40 Gop/s/mm² fixed-point operators for Brain Computer Interface in 65 nm CMOS

Libessart

Arzel

Lahuec

et al. 2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

The performance of non-invasive Brain-Computer Interface (BCI) depends on the computing performance of the system which solves the inverse problem. So the number of basic operations computed per second determines the BCI's resolution. Architecture with pipelined and parallelized flow is then required, and each operator in this architecture must be optimised to reach the highest possible computing performance. This paper presents the implementation of a fixed-point reciprocal and an inverse square root operators for the STMicroelectronics 65 nm CMOS technology. This paper follows previous works that optimise these operators on FPGA target. Each operator reaches a computing performance of about 40 Gop/s/mm 2 , which improves the literature results by a factor of four. Thus, this works fits well for portable and high performance BCI applications.

show abstract

Section: Related Workmentioning

confidence: 99%

40 Gop/s/mm² fixed-point operators for Brain Computer Interface in 65 nm CMOS

Libessart

Arzel

Lahuec

et al. 2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…We have shown in [12] that second order polynomial approximations must be used in order to guarantee faithful rounding (e.g. the reciprocal maximum error must be lower than 2 −25 ).…”

Section: Function Evaluationmentioning

confidence: 99%

“…We determined analytically (see [12] for details) the truncation error upper-bounds for the two multiplicationadditions and selected the coefficient formats that minimize the error bounds (in this case, Tp < 2 −29.3 ) given the above referred constraints:…”

Section: Function Evaluationmentioning

confidence: 99%

Efficient implementation of a single-precision floating-point arithmetic unit on FPGA

Jose

Silva

Neto

et al. 2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

This paper presents a single precision floating point arithmetic unit with support for multiplication, addition, fused multiply-add, reciprocal, square-root and inverse squareroot with high-performance and low resource usage. The design uses a piecewise 2 nd order polynomial approximation to implement reciprocal, square-root and inverse square-root. The unit can be configured with any number of operations and is capable to calculate any function with a throughput of one operation per cycle. The floatingpoint multiplier of the unit is also used to implement the polynomial approximation and the fused multiply-add operation. We have compared our implementation with other state-of-the-art proposals, including the Xilinx CoreGen operators, and conclude that the approach has a high relative performance/area efficiency.

show abstract

“…Extensive literature describing table-based polynomials exists. However, most focus on elementary functions [9], optimise the degree of the polynomial [10], support only up to 24 bits of precision [8], and use only fixed-point or only floatingpoint but not both data types [11], [12]. We consider these studies more on the theoretical side as they mainly focus on elementary functions whose highly optimised implementations are both available open-source [13] and are available in most vendor tools, so users are more likely to use ready-to-use implementations than to re-implement them using table-based methods.…”

Section: Introductionmentioning

confidence: 99%

Efficient Table-Based Polynomial on FPGA

Barbone

Kwaadgras

Oelfke

et al. 2021

2021 IEEE 39th International Conference on Computer Design (ICCD)

View full text Add to dashboard Cite

Field Programmable Gate Arrays (FPGAs) are gaining popularity in the context of scientific computing due to the recent advances of High-Level Synthesis (HLS) toolchains for customised hardware implementations combined with the increase in computing capabilities of modern FPGAs. As a result, developers are able to implement more complex scientific workloads which often require the evaluation of univariate numerical functions. In this study, we propose a methodology for tablebased polynomial interpolation aiming at producing area-efficient implementations of such functions on FPGAs achieving the same accuracy and at similar performance as direct implementations. We also provide a rigorous error analysis to guarantee the correctness of the results. Our methodology covers the forecast of resource utilisation of the polynomial interpolator and, based on the characteristics of the function, guides the developer to the most area-efficient FPGA implementation. Our experiments show that in the case of a radiation spectrum of a Black Body application based on evaluating Planck's Law, it is possible to reduce resource utilisation by up to 90% when compared to direct implementations not using table-based methods. Moreover, when only the kernels are considered, our method uses up to two orders of magnitude fewer resources with no performance penalties. Based on previous more theoretical works, our study investigates practical applications of table-based methods in the context of high performance and scientific computing where it is used to implement common but more complex functions than the elementary functions widely studied in the related literature.

show abstract

Very low resource table-based FPGA evaluation of elementary functions

Cited by 10 publications

References 9 publications

40 Gop/s/mm² fixed-point operators for Brain Computer Interface in 65 nm CMOS

40 Gop/s/mm² fixed-point operators for Brain Computer Interface in 65 nm CMOS

Efficient implementation of a single-precision floating-point arithmetic unit on FPGA

Efficient Table-Based Polynomial on FPGA

Contact Info

Product

Resources

About

Very low resource table-based FPGA evaluation of elementary functions

Cited by 10 publications

References 9 publications

40 Gop/s/mm2 fixed-point operators for Brain Computer Interface in 65 nm CMOS

40 Gop/s/mm2 fixed-point operators for Brain Computer Interface in 65 nm CMOS

Efficient implementation of a single-precision floating-point arithmetic unit on FPGA

Efficient Table-Based Polynomial on FPGA

Contact Info

Product

Resources

About

40 Gop/s/mm² fixed-point operators for Brain Computer Interface in 65 nm CMOS

40 Gop/s/mm² fixed-point operators for Brain Computer Interface in 65 nm CMOS