2004
DOI: 10.1023/b:alog.0000031435.96974.30
|View full text |Cite
|
Sign up to set email alerts
|

Very Low Voltage MOS Translinear Loops Based on Flipped Voltage Followers

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
13
0

Year Published

2007
2007
2012
2012

Publication Types

Select...
3
1
1

Relationship

0
5

Authors

Journals

citations
Cited by 16 publications
(13 citation statements)
references
References 6 publications
0
13
0
Order By: Relevance
“…An attractive characteristic of the topologies shown in Figures 6 and 7 is their capability for very low-voltage operation [3], [9]. This will be verified in the next section, where an LC elliptic filter will be functionally simulated.…”
Section: √ X-domain Building Blocksmentioning
confidence: 71%
See 2 more Smart Citations
“…An attractive characteristic of the topologies shown in Figures 6 and 7 is their capability for very low-voltage operation [3], [9]. This will be verified in the next section, where an LC elliptic filter will be functionally simulated.…”
Section: √ X-domain Building Blocksmentioning
confidence: 71%
“…Thus, the derived geometric-mean circuit is demonstrated in Figure 6. following expression [3]: If an inverted output current is required, this is achieved by using an extra currentmirror configuration at the output +Z; the output node is now denoted as −Z. The corresponding current squarer/divider block can be readily obtained by modifying the circuit in Figure 6 in such a way that the roles of terminals Z and X are interchanged.…”
Section: √ X-domain Building Blocksmentioning
confidence: 99%
See 1 more Smart Citation
“…A single power supply voltage V DD = 1.5 V is employed for biasing all the stages of the filter, while the dc current I o is chosen to be equal to 5 A. The FVFs used in geometric-mean and squarer/divider blocks [26] are biased at a dc current I B = 2 A, while the dc voltage V B has chosen to be equal to 0.8 V. Considering transistors models for the AMS 0.35 m S35 process, the MOS transistor aspect ratios for geometric-mean and squarer/divider blocks are summarized Tables II and III, respectively. The aspect ratios of nMOS transistors employed in integration, summation, and compression/expansion blocks were chosen to be 1.3/2 m. Thus, according to the formula R = 1/ √ 2K I o , the port resistance has a value equal to 34.48 k .…”
Section: Simulation Resultsmentioning
confidence: 99%
“…According to this, the geometric mean and squarer/divider blocks are given in Figures 11 and 12. An attractive characteristic of these topologies is their capability for very low-voltage operation [30,31]. In both configurations, the second-order translinear loops are established by the transistors Mn1-Mn4, while the employed FVFs are formed by the transistors Mn5, Mn7, and the dc current source I B .…”
Section: Srd Integrator Blocksmentioning
confidence: 99%