VFloat

Xiao-jun, Wang; Leeser, Miriam

doi:10.1145/1839480.1839486

Cited by 42 publications

(4 citation statements)

References 40 publications

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“…al. [33], based on Hung's [16] approach, has reported a custom precision floatingpoint division on a Virtex-IIPro FPGA for a 41-bit (10-bit exp and 29-bit mantissa) floating point format. The area complexity is quite large, with a requirement of 62 BRAMs with 125 MHz frequency, and is further reported to have precision loss.…”

Section: Comparison With Series Expansion (Se) Methodsmentioning

confidence: 99%

“…This method requires large amounts of logic (area) in terms of memory and multipliers, but is better in terms of latency and performance vis-a-vis digit recurrence method. The approximation method comes in to play when the desired level of accuracy is low, and generally falls in two categories: Direct Approximation (using look-up tables) and linear/polynomial approximation (using small look-up tables and/or partial product arrays) [16,19,33]. All these methods primarily vary in terms of area, speed, latency and/or accuracy, and mainly targeted the normalized implementation.…”

Section: Introductionmentioning

confidence: 99%

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Series Expansion based Efficient Architectures for Double Precision Floating Point Division

Jaiswal

Cheung

Balakrishnan

et al. 2014

Circuits Syst Signal Process

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Floating-point division is a complex operation among all floating-point arithmetic; it is also an area and performance dominating unit. This paper presents double-precision floating-point division architectures on FPGA platforms. The designs are area-optimized, running at higher clock-speed, with less latency, and are fully pipelined. Proposed architectures are based on the well-known Taylor-series expansion, using relatively smaller amount of hardware in-terms of memory (initial look-up table), multiplier blocks and slices. Two architectures have been presented with various trade-offs amongst area, memory and accuracy. Designs are based on the use of the partial block multipliers (PBM), in order to reduce hardware usage while minimizing the loss of accuracy. All the implementations have been targeted and optimized separately for different Xilinx FPGAs to exploit their specific resources efficiently. Compared to previously reported literature, the proposed architectures require less area, reduced latency, with the advantage of higher performance gain. The accuracy of the designs have been both theoretically analyzed and validated using random test cases.

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Section: Comparison With Series Expansion (Se) Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Series Expansion based Efficient Architectures for Double Precision Floating Point Division

Jaiswal

Cheung

Balakrishnan

et al. 2014

Circuits Syst Signal Process

View full text Add to dashboard Cite

show abstract

“…• Rounding is required in order to trim back the 106-bit mantissa multiplication result to 53-bit only. This can be done as per IEEE standard [16]- [17].…”

Section: Floating Point Multiplicationmentioning

confidence: 99%

Resource Efficient Single Precision Floating Point Multiplier Using Karatsuba Algorithm

Gowreesrinivas

Samundiswary

2018

IJEEI

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In floating point arithmetic opearations, multiplication is the most required operation for many signal processing and scientific applications. 24-bit length mantissa multiplication is involved to obtain the floating point multiplication final result for two given single precision floating point numbers. This mantissa multiplication plays the major role in the performance evaluation in respect of occupied area and propagation delay. This paper presents the design and analysis of single precision floating point multiplication using karatsuba algorithm with vedic multiplier with the considering of modified 2x1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing techniques. Further, the performance analysis of single precision floating point multiplier is analyzed in terms of area and delay using Karatsuba Algorithm with different existing techniques such as 4x1 multiplexers and 3:2 compressors and modified techniques such as 2x1 multiplexers, 4:2 compressors. From the simulation results, it is observed that single precision floating point multiplication with karatsuba algorithm using modified 4:2 compressor with XOR-MUX logic provides better performance with efficient usage of resources such as area and delay than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator.

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“…Most embedded systems, System-on-Chip (SoC) and transmission systems are implemented using either fixed point, floating point or hybrid number systems wherein fixed [1] [2] and floating point numbers [3] [4] can be used together in the same chip [5]- [7]. The IEEE754-1985 standard was released for binary floating point arithmetic with some new features such as better precision, range and accuracy [8].…”

Section: Introductionmentioning

confidence: 99%

Open Source Synthesis and Verification Tool for Fixed-to-Floating and Floating-to-Fixed Points Conversions

Aslan¹,

Mohammad²,

Salamy³

2016

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An open source high level synthesis fixed-to-floating and floating-to-fixed conversion tool is presented for embedded design, communication systems, and signal processing applications. Many systems use a fixed point number system. Fixed point numbers often need to be converted to floating point numbers for higher accuracy, dynamic range, fixed-length transmission limitations or end user requirements. A similar conversion system is needed to convert floating point numbers to fixed point numbers due to the advantages that fixed point numbers offer when compared with floating point number systems, such as compact hardware, reduced verification time and design effort. The latest embedded and SoC designs use both number systems together to improve accuracy or reduce required hardware in the same design. The proposed open source design and verification tool converts fixed point numbers to floating point numbers, and floating point numbers to fixed point numbers using the IEEE-754 floating point number standard. This open source design tool generates HDL code and its test bench that can be implemented in FPGA and VLSI systems. The design can be compiled and simulated using open source Iverilog/GTKWave and verified using Octave. A high level synthesis tool and GUI are designed using C#. The proposed design tool can increase productivity by reducing the design and verification time, as well as reduce the development cost due to the open source nature of the design tool. The proposed design tool can be used as a standalone block generator or implemented into current designs to improve range, accuracy, and reduce the development cost. The generated design has been implemented on Xilinx FPGAs.

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VFloat

Cited by 42 publications

References 40 publications

Series Expansion based Efficient Architectures for Double Precision Floating Point Division

Series Expansion based Efficient Architectures for Double Precision Floating Point Division

Resource Efficient Single Precision Floating Point Multiplier Using Karatsuba Algorithm

Open Source Synthesis and Verification Tool for Fixed-to-Floating and Floating-to-Fixed Points Conversions

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