VHDL-based distributed fault simulation using SAVANT

Baucom, R.J.; DeLong, T.A.; Smith, D.T.; Johnson, B.W.; Hanna, James P.

doi:10.1109/naecon.1998.710203

Cited by 3 publications

(1 citation statement)

References 5 publications

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“…Considering the prevalence of hardware description languages throughout all phases of the IC design process, defect modeling with VHDL is a compelling idea that has been evolving steadily over the past several years [5][6][7][35][36][37][38][39][40][41][42][43][44][45]. VHDL is a popular and standardized hardware description language, used extensively in design specification, analysis, synthesis, and functional test generation.…”

Section: Defect-injectable Vhdl Cell Modelsmentioning

confidence: 99%

Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries

Shaw¹,

Al-Khalili

Rozon

2006

Integration

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Section: Defect-injectable Vhdl Cell Modelsmentioning

confidence: 99%

Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries

Shaw¹,

Al-Khalili

Rozon

2006

Integration

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Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models

Shaw¹,

Al-Khalili

Rozon

2002

Integration

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Plataforma de co-emulação de falhas em circuitos integrados.

Sarmiento¹,

Arturo²

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A platform and a technique to improve stuck-at fault grading efficiency through the use of hardware co-emulation is presented. IC manufacturers are always seeking for new ways to test their devices in order to deliver parts with zero defects to their customers. Scan is a well known technique that attains high fault coverage results with efficiency. Demands for new features motivate the creation of high complex systems with a mixture of analog and digital blocks with a communication interface that is difficult to cover with scan patterns. In addition, the logic that configures the chip for each of the different test modes, some BIST memory interfaces, asynchronous clock dividers or generators, among others, are examples of circuits that are blocked or have few observation/control points during scan. A FPGA basedplatform that uses heterogeneous models to emulate digital, analog and memory blocks for fault grading patterns on complex systems is described. Also introduced in our proposal are four types of models that can be used with FPGAs, and the results of applying our fault co-emulation technique to some benchmark circuits including ISCAS89, ADC, iopads and memory controllers.

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VHDL-based distributed fault simulation using SAVANT

Cited by 3 publications

References 5 publications

Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries

Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries

Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models

Plataforma de co-emulação de falhas em circuitos integrados.

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