VHDL generation from SDL specifications

Abstract

The aim of this paper is to present an approach that allows the generation of VHDL from system level specifications in SDL. Our approach overcome the main known problem encountered by previous work which is the communication between different processes. We allow SDL communication to be translated into VHDL for synthesis. This is made possible by the use of an intermediate form that support a powerful communication model which enable the representation in a synthesis oriented manner of most communication schemes. This intermediate form allows the refinement of the system in order to obtain the desired solution. The main refinement step, called communication synthesis, is aimed at fixing the protocol and the interface used by the different processes to communicate. The refined specification is translated into VHDL for synthesis using existing CAD tools. We illustrate the feasibility of our approach through two SDL to VHDL translation examples.

Formal system design based on the synchrony hypothesis, functional models, and skeletons

“…Such a communication model forms the base for languages as SDL [17,19], VHDL [18], or SpecCharts [15]. While this model serves as a good implementation model, due to its closeness to architecture, we argue, that it is not a good choice for a functional system model.…”

A generator tool for Carry Look-ahead Adders (CLA)

“…Of course, these tools can be used to create HDL descriptions of typical adders but for a certain range of bitwith and vectors. Daveau, Marchioro, Valderrama and Jerraya [3] present a way from SDL models to VHDL generation, but their work focuses only on the specification and there is no EDA tool. Lily Kanoriya, Aparna Gupta, Dr. Soni Changlani give a method of designing an IC layout using 90nm technology but they don't design any tool for this.…”

Parallel and Distributed Processing

“…As reported in [2,7,9,19,20,21], SDL hardware descriptions are often translated into VHDL. This allows SDL to be used for high-level hardware description, coupled with common tools for hardware synthesis and further analysis.…”