VHDL structural model visualization

Abstract

Nowadays the digital systems design is almost exclusively realized using hardware description languages (HDL). In Europe, the VHDL (Very-High-Speed Integrated Circuits HDL) is the most widely used HDL. Although HDLs brought a lot of advantages into the design process, the HDL structural models, especially on register transfer and lower layers, are harder to read than the previously used schematic representations. That is why a lot of commercial EDA (Electronic Design Automation) systems include some kind of visualization tool enabling to represent a model structure in a graphical form. However, these systems are usually too complex and expensive for the education purpose. In this case simple, easy to use visualization tool would be more appropriate. The paper deals with the problem of the structural models visualization as well as with the design and implementation of the visualization tool devoted to the VHDL structural models visualization. The presented tool offers the possibility to display the schematic view corresponding to the input VHDL model, edit the schematic layout, print it or export it to an image file. The tool preserves the model hierarchy and enables to easily switch among the respective levels. It represents an useful tool in the process of the VHDL structural model verification and debugging as well as for documentation purposes.

Extensible framework for graphical representation of HDL models and Simulation Results

“…Altogether fourteen HDL models of varying complexity were used for this purpose including for example counters, various converters, busses, simple processors, etc. The results were manually checked against the HDL/XHDL inputs and in case it was possible compared to the results provided by available solutions [7][8][9] concerning the functionality, performance, and quality of visualization. As it was expected the most time critical part of the whole process was the modules, ports, and signals distribution.…”

“…The topic has been studied at the Faculty of Informatics and Information Technologies, Slovak University of Technology in Bratislava as well. For example in [7] authors dealt with the visualization of digital systems described in VHDL. On the other hand, Verilog models visualization is supported in the tool discussed in [8] and SystemC models support is presented in [9].…”

“…The solutions [7][8][9] have already been used in the educational process for several years so the feedback and experience from students was analyzed as well to specify the requirements for the new system. The key requirements include support for several HDLs (at least the basic three), the possibility to extend support to other languages, visualization of model structure based on hierarchical levels in a well-arranged form, model simulation with simulation results displayed within the structure.…”

“…To design the HDL visualization framework the available solutions [1][2][3][4][5][6][7][8][9] have been thoroughly studied and tested. The solutions [7][8][9] have already been used in the educational process for several years so the feedback and experience from students was analyzed as well to specify the requirements for the new system.…”

“…In case of VHDL and Verilog the data extraction is based on source code analysis that is performed by separate parser for each language generated by the ANTLR parser generator [10]. The input grammars and parsers for the languages were inspired by [7] and [8]. The resulting modules VHDL2XML and Verilog2XML generate the XHDL data in several steps that had to respect the language specifics and therefore differ a bit based on the language.…”