Via Interconnections for Half-Inch Packaging of Electronic Devices Using Minimal Fab Process Tools

Abstract

Reliability of a laser-via formation process for Fan-Out Wafer Level Packaging (FOWLP) technology was evaluated using Minimal Fab (MF) that is cleanroom-less and uses a half inch wafer. After a die-bonding and a compression molding process of a half-inch Si wafer, the laser-vias were formed with a diameter of 150 m by irradiation of an ultraviolet (UV) pulsed laser beam. The measured thickness of the epoxy mold compound (EMC) was 93.9 m of average with 1.9% of the variation at 1  in the half-inch wafer. The bottom diameter of the vias was 51.8 m and 9.0% of the variation at 1 . In order to evaluate the contact-resistance of the vias, Cross-Bridge Kelvin Resistor (CBKR) test-structures were fabricated by the die-bonding the Si wafer with Al or Cu/Ti pads to a 42 alloy substrate, the compression molding, the laser-via, and the redistribution layer (RDL) formation. In case of the Al pads, the via conduction was obtained only in the outer peripheral area. On the other hand, in case of the Cu/Ti pad, the all via conductions were obtained. The high-yield via-interconnections were achieved by using Cu/Ti pads.