Vias-last process technology for thick 2.5D Si interposers

Vick, Erik; Goodwin, Scott; Cunnigham, Garry; Temple, Dorota

doi:10.1109/3dic.2012.6262990

Cited by 10 publications

(6 citation statements)

References 2 publications

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“…This TSV approach is relatively mature [1][2][3][4], conceptually straight-forward, and inherently compatible with the WLVP requirements discussed above. As shown in the general schematic in Figure 1, TSVs are etched from the backside of the device wafer, terminating (or landing) on the backside of the lowest level of the frontside metallization.…”

Section: Standard Low Aspect Ratio Tsv Approachmentioning

confidence: 93%

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Demonstration of low cost TSV fabrication in thick silicon wafers

Vick

Temple

Anderson

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Low cost wafer-level chip-scale vacuum packaging (WLCSVP) imposes unique constraints on potential implementation of through-silicon vias (TSVs). A WLCSVP requires a relatively thick substrate to prevent mechanical failure. Two approaches for integrating TSVs in thick silicon wafers have been successfully demonstrated.Both approaches enable TSV formation from the backside of a device wafer and are compatible with the requirements of subsequent packaging operations. We achieved low contact resistance between TSVs and frontside Ti/Cu and Al metallization, while demonstrating high isolation resistance and high TSV yield.

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Section: Standard Low Aspect Ratio Tsv Approachmentioning

confidence: 93%

“…Compared to wire-bond interconnections, TSVs offer the potential for higher density input/output (I/O) configurations as well as a significant reduction of the size and weight of the package [3][4][5][6]. The combination of both can translate into more functionality and a smaller overall form factor.…”

Section: Introductionmentioning

confidence: 99%

Demonstration of low cost TSV fabrication in thick silicon wafers

Vick

Temple

Anderson

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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“…As a result, recent work focused on demonstrating a vias-last approach comprised of unfilled (or barrel coated) vias (examples in Figure 3) with smaller TSV dimensions (80 µm TSV diameter) in thinner (500 µm thick) 6" wafers that maintained the 6:1 via AR of our previous studies [2]. As reported previously, the vias-last process flow basically consisted of a backside via etch, via passivation, and via metallization step [2,5]. However, to make good electrical contact to a frontside metal (e.g.…”

Section: Through-si Via Process Modulesmentioning

confidence: 99%

Process integration and testing of TSV Si interposers for 3D integration applications

Lannon

Hilton

Huffman

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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Two 3D Si interposer demonstration vehicles containing through-Si vias (TSVs) were successfully fabricated using integration of two different TSV formation and multilevel metallization (MLM) process modules.The first Si interposer vehicles were made with a dual damascene frontside MLM (5 levels), backside TSV (unfilled, vias-last), and backside metallization (2 levels) process sequence on standard thickness 6" wafers. The front-side MLM was comprised of 4 metal routing layers (2 µm Cu with 2 µm oxide interlayer dielectric) and 1 metal pad layer. Electrical yield as high as 100% was obtained on contact chain test structures containing 26,400 vias between the front-side MLM layers, while the average contact resistance between the dual damascene levels was < 4 mΩ per via. TSV dimensions of 100 and 80 µm diameter and 6:1 aspect ratio were investigated. DRIE bottom clear process conditions were optimized for each via dimension to produce 100% yield on TSV contact chains with up to 540 vias. The optimized DRIE conditions also resulted in TSV resistance below 30 mΩ and sufficient TSV isolation resistance (>100MΩ/via at 3.3V) for the target application. Functional testing of two die (4 cm x 3.7 cm die size) showed that 99% of the functional circuit path nets had acceptable continuity and isolation. The second Si interposer vehicles were fabricated using a vias-first TSV (filled, blind vias), waferlevel packaging (WLP) front-side MLM (2 levels), wafer thinning (via reveal), and WLP-MLM (1 level) process sequence on stock 6" wafers. Via dimensions for the viasfirst interposers were 50 µm diameter x 315 µm depth or 80 µm diameter x 315 µm depth (6:1 or 4:1 aspect ratios). The front and backside MLM was formed with a 2 µm Cu routing layer and one of two spin-on dielectrics (polyimide or ALX) for evaluation of polymer dielectric process compatibility with Cu-filled TSVs and thinned wafer processing. Details of the process modules and process integration required to realize the TSV Si interposers are described.

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“…Second, in-package DRAMs do not require on-die termination [66]. First, in-package graphics memory has a wide memory interface, which enables memory power reduction without degrading the peak memory bandwidth.…”

Section: D-stacked Gpu Memorymentioning

confidence: 99%