Virtual contrast enhancement intelligent illumination adjustment processing with field programmable gate array based camera systems for imaging applications enhancing contrast in multi AOI applications

Abstract

Virtual contrast enhancement allows a high speed illumination sequence set optimization for high precision measurement tasks. Therefore an FPGA controls the illumination and processes a captured image stack inside the camera.

High speed embedded imaging architectures for multichannel imaging

“…So with the use of these indexes a significant address in the RAM is defined. From the beginning of the design two RAM circuits were planned to separate fast processing from sequential tasks like: administration of the system, communication with asynchrony devices like motors [8] or lighting controls [6]. After the processing is done in the IPU, the IPU handovers a control signal to the asynchrony RISC processing unit.…”

“…Therefore an automation algorithm was developed to lead the operator to good measurement results. This application was modified and implemented in an FPGA to increase the processing speed and add a virtual contrast enhancement feature [5,6]. For this application [7] consider a special platform which consists of an FPGA-architecture which is equipped with a one port DDR2 memory interfacing system.…”