Virtual logic netlist: Enabling efficient RTL analysis

Heterogeneity aware power abstractions for dynamic power dominated FinFET‐based microprocessors

“…With clock gating gaining importance, more solutions are being pursued for improving it. Currently, there is enhanced focus on performing clock‐activity computation, analyses and reduction throughout the design cycle [9, 16]. Newer techniques are being employed for early design analysis to enable rapid RTL clock and memory activity takedown.…”

“…Principles of logic‐level verification, trace import and simulation replay, logic debug and virtual logic netlist‐based RTL analysis are tied together to build this new platform [9, 16]. The details of this new platform for clock and memory gating analyses are given in Fig.…”