Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization

Boley, Jim; Beshay, Peter; Calhoun, Benton H.

doi:10.1109/tvlsi.2014.2385832

Cited by 2 publications

(1 citation statement)

References 16 publications

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“…We discussed various techniques such as the use of low-leakage devices (e.g., ULL in DDC or High-V T ) and smaller bank size to reduce the numbers of bitcells per bitline [47] to minimize the leakage. After optimizing the SRAM bicell array leakage, the peripheral circuit components require leakage mitigation techniques.…”

Section: Enabling the Next Generation Bsns Socmentioning

confidence: 99%

Ultra-Low Power and Reliable SRAM for Systems-on-Chip

Patel¹

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The number of ubiquitous sensors has increased to more than double the human population and is expected to continue growing in the future. The pervasive use of sensors for applications such as personal healthcare and the Internet of Things (IoT) presents a growing sustainability challenge concerning the availability and accessibility of power sources. With 50 billion less BSN system. First, we explore different design knobs for an optimal SRAM design targeting ULP applications. These knobs include leveraging advanced fabrication technology, optimal device selection, circuit design techniques, and architectural techniques. Next, we evaluate the efficacy of different read and write peripheral assist techniques for improving reliability and energy efficiency of subthreshold SRAMs and provide stability, power, and performance trade-offs for system level optimization. The result of various optimization approaches resulted in a leakage and energy optimized SRAM operating over with leakage power reduced to 1.5 pW/bit while consuming only 6.24 pJ/access energy that is 40% more efficient than the previous version. To address a wide range of IoT applications with energy optimization, we propose a Canary sensor based minimum supply voltage (V M IN) tracking with optimal selection of the peripheral assist techniques. Later, we address the reliability issue at subthreshold operation using a process, voltage, and temperature (PVT) variation mitigation controller. Finally, the impact of the radiation-induced soft error is evaluated to provide a comprehensive study on reliability for the ULP SRAM at scaled V DD. Dedicating what all I learn in my life to 'Gurus' in my life-for enlightening my life with the knowledge, My Parents-for always giving me the courage to achieve impossible, My Wife-Pooja-for her unwavering love and motivation Meaning: Lead me from the unreal to the real; from darkness(ignorance) to light(knowledge); and from death to immortality. iv v Besides my life at the lab doing the research work, I immensely enjoyed my stay in Charlottesville. I am very much grateful to my neighbors for their pleasant company during my stay. I am also grateful to the members of Swadhyay Parivar for their selfless love. Last but never the least, I would like to thank my family members. I am very grateful for my parents, Naranbhai and Induben, for their continuous support and motivation for vii pursuing higher education. Especially, I thank my mother for always keeping me in her prayer while my father for giving me the courage to achieve whatever seems impossible to me. I thank my sister-Rinku-for her sisterly love. I cannot encompass my gratitude to my wife, Pooja, with the words for her support. She always been a lovely wife with continuous support. I am also indebted to almighty God for his blessing of two beautiful children, Samyak and Swara-my best stress busters! I cannot image myself completing my Ph.D. without the help of all these three-my wife and my kids-Thank you so much!

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Section: Enabling the Next Generation Bsns Socmentioning

confidence: 99%