Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions

Abstract

Abstract. Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include Architecturally Visible Storage (AVS), compiler-controlled memories accessible exclusively to the ISEs. Unfortunately, the usage of AVS memories creates a coherence problem with the data cache. A multiprocessor coherence protocol can solve the problem, however, this is an expensive solution when applied in a uniprocessor context. Instead, we can solve the problem by modifying the cache controller so that the AVS memories function as extra ways of the cache with respect to coherence, but are not generally accessible as extra ways for use under normal software execution. This solution, which we call Virtual Ways is less costly than a hardware coherence protocol, and eliminate coherence messages from the system bus, which improves energy consumption. Moreover, eliminating these messages makes Virtual Ways significantly more robust to performance degradation when there is a significant disparity in clock frequency between the processor and main memory.

Architecture support for custom instructions with memory operations

“…In the GARP [13], VEAL [8] and OneChip [7] systems, the compiler needs to insert some special instructions to ensure all preceding memory operations have completed before launching the custom instruction. Systems with architecturally visible storage (AVS) [5,14] also depend on the compiler for synchronization.…”

“…The CI to be executed launches three memory operations: a read from location M 2 and writes to M 1 and M 3. For previous work [7,14], the CI needs to at least wait until the addresses of all preceding memory operations are computed before proceeding; this is enforced by inserting synchronization instructions before the CI. We overcome this limitation by modifying the core's microarchitecture.…”

Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions

“…Way Stealing does not add extra memory elements to the system and, therefore, is memory coherent and consistent in presence of caches; unlike past solutions to the coherence problem for AVS-enhanced ISEs [19][20][21], Way Stealing requires more stringent boundary conditions. These conditions do not endanger its generality, but do require extensive, yet non-critical, changes to the processor pipeline and data cache.…”

“…1(a) shows a RISC processor pipeline augmented with AVS-enhanced ISEs; the hardware realization of an ISE is called an Application Specific Custom Unit (ASCU), and it executes in parallel with the ALU stage of the pipeline. Without loss of generality, if Virtual Ways [19,21] is applied to ensure coherence between the processor's data cache and the AVS memory, then the tag portion of the AVS memory must be visible to the data cache (to provide coherence), while the data portion is only available to the ASCU.…”

“…The compiler disambiguates AVS-resident data structures and inserts DMA transfers to load them from main memory into the AVS and store them back when the ISEs are finished. Unfortunately, this creates a coherence problem between the AVS and the processor's data cache, which can be solved using a hardware coherence protocol [19,20] or a specialized cache controller [19,21].…”