Visual-Trace Simulation of Concurrent Finite-State Machines for Validation and Model-Checking of Complex Behaviour

Coleman, Robert A.; Estivill‐Castro, Vladimir; Hexel, René; Lusty, Carl

doi:10.1007/978-3-642-34327-8_8

Cited by 4 publications

(8 citation statements)

References 13 publications

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“…The use of Boolean expression to label transitions has a series of advantages: it simplifies semantics, facilitates scheduling and handling of concurrency [9,10,12] and enables validation and formal verification [11]. This produces rapid development and simulation of robot behaviours [5].…”

Section: The Logic-labeled Finite-state Machine Modelmentioning

confidence: 99%

High Performance Relaying of C++11 Objects across Processes and Logic-Labeled Finite-State Machines

Estivill‐Castro

Hexel

Lusty

2014

Simulation, Modeling, and Programming for Autonomous Robots

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We present gusimplewhiteboard, a software architecture analogous to ROS:services and ROS:messages, that enables the construction and extremely efficient inter-process relaying of message-types as C++11 objects, All gusimplewhiteboard objects reside in shared memory. Moreover, our principle is to use idempotent message communication, in direct contrast to previously released platforms for roboticmodule communication, that are based on an event-driven subscriber model that queues and multi-threads. We combine this with compiled, time-triggered, logic-labeled finite state machines (llfsms) the are executed concurrently, but scheduled sequentially, in an extremely efficient manner, removing all race conditions and requirements for explicit synchronisation. Together, these tools enable effective robotic behaviour design, where arrangements of llfsms can be organised as hierarchies of machines and submachines, enabling composition of very complex systems. They have proven to be very powerful for Model-Driven Development, capable of simulation, validation, and formal verification.

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Section: The Logic-labeled Finite-state Machine Modelmentioning

confidence: 99%

High Performance Relaying of C++11 Objects across Processes and Logic-Labeled Finite-State Machines

Estivill‐Castro

Hexel

Lusty

2014

Simulation, Modeling, and Programming for Autonomous Robots

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“…By using sequential scheduling we maintain concurrency, and the models produced with the logic-labelled FSMs can be verified using modelchecking technology (NuSMV) within a matter of seconds (Estivill-Castro et al, 2012c;Coleman et al, 2012), while for the same case studies, but using Behavior Trees -which have explicit notation for spawning parallel threads -require several days of CPU to verify equivalent properties (Grunske et al, 2011).…”

Section: Finite-state Machinesmentioning

confidence: 99%

“…Perhaps most importantly, we have been able to uncover hidden complexities and errors in prior modelling of software engineering problems (Winter and Yatapanage, ; Grunske et al, 2011). To this end, we have both performed formal model checking (Estivill-Castro et al, 2012c) as well as simulation of system behaviour (Coleman et al, 2012).…”

Section: Examplesmentioning

confidence: 99%

“…lustrates the language independence and platform independence of this MDD approach. The model can also be simulated (Coleman et al, 2012) and has been subjected to fault injection to produce FMEA tables for the analysis of failure-robustness (Estivill-Castro et al, 2012c;Estivill-Castro et al, 2012a).…”

Section: Examplesmentioning

confidence: 99%

“…Two examples where this approach has been successful in performing simulation, model-checking, and execution across platforms, are a Mine Pump and an Industrial Press (Coleman et al, 2012;Estivill-Castro et al, 2012c;Estivill-Castro et al, 2012a). A fourth case study where simulation and modelchecking has been very effective has been the Ambulatory Infusion Pump (Estivill-Castro et al, 2012b).…”

Section: Examplesmentioning

confidence: 99%

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Arrangements of Finite-state Machines - Semantics, Simulation, and Model Checking

Estivill‐Castro¹,

Hexel²

2013

Proceedings of the 1st International Conference on Model-Driven Engineering and Software Development

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We propose a contrasting approach to the main stream direction that UML and STATEMATE have recently taken when using finite-state machines (FSMs) to model behaviour. That is, rather than the event-driven model that is currently dominant, we suggest to adopt a model of time, a synchronous model. We do support concurrency in our arrangements of FSMs but eliminate the sources of unpredictable threads of execution. Currently, such capacity of the dominant semantics actually results in the need to create many language constructs to regulate threads that, in many cases, even result in imprecise semantics, hampering their use for model-driven development (MDD). By allowing transitions to only be labeled by statements of logic and by executing the machines with an offline schedule, we obtain a simpler language, with less burden for the developer. This creates far reaching potential for accompanying tools, such as integrated development environments, simulators, and even formal verification through model-checking. Model-checking is of particular importance as MDD becomes ubiquitous. Model-checking is possible for our FSMs as we do not need to consider all possible combinations of progress of each of the many threads that the event-driven alternative requires.

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Efficient Modelling of Embedded Software Systems and their Formal Verification

Estivill‐Castro

Hexel

Rosenblueth³

2012

2012 19th Asia-Pacific Software Engineering Conference

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We propose vectors of finite-state machines whose transitions are labeled by formulas of a common-sense logic as the modelling tool for embedded systems software. We have previously shown that this methodology is very efficient in producing succinct and clear models (e.g., in contrast to plain finite-state machines, Petri nets, or Behavior Trees). We show that we can capture requirements precisely and that we can simulate and validate the models. We can, therefore, directly apply Model-Driven Engineering and deploy the models into software for diverse platforms with full traceability of requirements. Moreover, the sequential semantics of our vector of finite-state machines enables model-checking, formally establishing the correctness of the model. Finally, our approach facilitates systematic Failure Modes and Effects Analysis (FMEA) for diverse target platforms. We demonstrate the effectiveness of our methodology with several examples widely discussed in the software engineering literature and compare this with other approaches, showing that we can prove more properties, and that some claims about verification in such approaches have been exaggerated or are incomplete. Index Terms-Software testing, verification and validation, formal methods in software engineering, software requirements engineering. model-driven engineering.

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Visual-Trace Simulation of Concurrent Finite-State Machines for Validation and Model-Checking of Complex Behaviour

Cited by 4 publications

References 13 publications

High Performance Relaying of C++11 Objects across Processes and Logic-Labeled Finite-State Machines

High Performance Relaying of C++11 Objects across Processes and Logic-Labeled Finite-State Machines

Arrangements of Finite-state Machines - Semantics, Simulation, and Model Checking

Efficient Modelling of Embedded Software Systems and their Formal Verification

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