Visualization of Plasma Etching Damage of Si Using Room Temperature Photoluminescence and Raman Spectroscopy

Jin

et al. 2015

Room temperature photoluminescence (RTPL) spectroscopy and Raman spectroscopy were examined as in-line monitoring techniques for characterizing the interface characteristics of ultra-thin (∼7.2 nm) stacked dielectric films (SiN/SiO 2 ) on 300 mm Si wafers. To investigate the effect of the stacked dielectric films on electronic properties and lattice stress of Si beneath the films, RTPL and Raman signals were measured under various excitation wavelengths with different probing depths. Changes of interface characteristics (mainly, electronic properties and lattice stress of Si beneath the films) of the stacked dielectric films and the Si wafer were investigated using various specimens prepared by different deposition techniques and conditions. The overall interface characteristics of the SiN/SiO 2 /Si specimens was found to be very dependent on the SiN deposition technique and process conditions. As the stoichiometry of SiN films change from N-rich to Si-rich conditions, the RTPL signal becomes weaker, indicating the change of electronic properties at the SiN/SiO 2 /Si interface. Within-wafer and wafer-to-wafer variations of the SiN/SiO 2 /Si interface characteristics were successfully characterized by RTPL and Raman spectroscopy under various excitation wavelengths.Other characterization results such as film thickness from ellipsometry, film stress from wafer curvature and film composition from Auger electron spectroscopy (AES) were also discussed. Advanced metal-oxide-semiconductor (MOS) and metalinsulator-semiconductor (MIS) devices employ ultra-thin dielectric film(s) as gate dielectrics. The physical dimensions are typically on the order of several nanometers. Pure SiO 2 or combinations of SiN and SiO 2 films are typically used. Both physical thickness and effective oxide thickness (EOT) are less than 10 nm.1-2 High dielectric constant materials (high-k dielectrics) and metal gates are also frequently used. Low dielectric constant materials (low-k dielectrics) are used as inter-metal dielectrics (IMD) and inter-layer dielectrics (ILD) with Cu interconnects to reduce RC constants (i.e, RC delay) and improve device operation speed.3 As devices scale to smaller size, the complexity of device structures as well as the number of interfaces in dielectric films increases. Proper understanding, monitoring and control of the dielectric/Si interface become very important.Physical dimensions of ultra-thin dielectric film(s) on Si wafers are typically measured using ellipsometry and occasionally verified by high resolution cross-section transmission electron microscopy (HRXTEM). Conventional interface characterization techniques include chemical characterization and electrical characterization. Chemical properties are typically evaluated using Auger electron spectroscopy (AES), secondary ion mass spectroscopy (SIMS) and X-ray photoelectron spectroscopy (XPS).4-6 Films stress is often monitored in blanket Si wafers by measuring the curvature, and its direction, before and after film deposition and treatment.7-10 The stoic...

Section: N77mentioning

confidence: 99%

Room Temperature Photoluminescence and Raman Characterization of Interface Characteristics of SiN/SiO₂/Si Prepared under Various Deposition Techniques and Conditions

Yoo¹,

Jin

et al. 2015

“…16 Other RTPL studies also showed significant drops in RTPL intensities in SiO 2 /Si with UV exposure during routine optical characterization and ionic charge exposure in air during Corona charge-based, non-contact electrical (I-V and C-V) characterization. 19 All of these left permanent damage to the Si lattice and/or SiO 2 /Si integrity which can impact electrical properties.…”

Section: Resultsmentioning

confidence: 89%

“…Multiwavelength RTPL intensity P317 measurements of SiO 2 /Si wafers showed very promising features as a non-contact optical characterization technique for probing electrical properties of dielectric/Si structures. [16][17][18][19][20][21][22][23] The chamber-to-chamber RTPL intensity comparisons between the qualified chamber (Chamber B-1) and disqualified chamber (Chamber A) showed ∼20% reduction. The gas flow pattern change within the qualified chamber (Chamber B-1 and B-2) showed how gas flow impacts SiO 2 thickness distribution and RTPL intensity distribution on Si wafers.…”

Section: Resultsmentioning

confidence: 99%

Investigation of Plasma Enhanced Chemical Vapor Deposition Chamber Mismatching by Photoluminescence and Raman Spectroscopy

Cho

et al. 2015

Slight differences between supposedly identical process chambers are a well known problem in semiconductor manufacturing. In particular, individual plasma-aided process chambers are difficult to characterize and tune to match each other because plasma is a non-equilibrium state and can leave its "footprint" in subtle ways on a wafer. This process chamber mismatching phenomena was investigated in a dual chamber, commercial, high density plasma chemical vapor deposition system by monitoring SiO 2 /Si interface quality using multiwavelength room temperature photoluminescence and Raman spectroscopy. Effects on the SiO 2 /Si interface quality, from altering the gas flow pattern in the plasma process chamber, are also studied.

“…The details of the system and its applications have been published elsewhere. [7][8][9][10] No measurable RTPL signal was observed from most of SiO 2 /Si wafers under 532 nm excitation. For 650 nm excitation, the laser power at the wafer surface was 20 mW and exposure time was 1.0 s per point.…”

Section: Methodsmentioning

confidence: 99%

Ultra-Thin SiO₂/Si Interface Quality In-Line Monitoring Using Multiwavelength Room Temperature Photoluminescence and Raman Spectroscopy

Yoo¹,

Jin

et al. 2014

Multiwavelength room temperature photoluminescence (RTPL) and Raman spectroscopy were proposed as in-line monitoring techniques for characterizing the dielectric/Si interface. As an application example, ∼7.0 nm thick ultra-thin SiO 2 films on 300 mm Si wafers, prepared by various oxidation techniques and conditions, were characterized using multiwavelength RTPL and Raman spectroscopy. Specifically, overall quality of the ultra-thin SiO 2 /Si interface (including passivation characteristics) and Si lattice stress beneath SiO 2 films are investigated. The overall SiO 2 /Si interface quality was seen to be very dependent on oxidation technique and process conditions. Within wafer and wafer-to-wafer variations of SiO 2 /Si interface quality were successfully characterized by RTPL and Raman spectra measurements. For electrical analysis of SiO 2 /Si-based structures, non-contact corona charge-based, in-line (capacitance-voltage (C-V) and stress induced leakage current (SILC)) measurements were performed and compared with RTPL and Raman characterization results. Surprisingly, significant variations in RTPL intensity at and near the corona charge-based measurement sites, indicated that the corona-based electrical measurement technique, though non-contact, was indeed invasive. The effect of corona-charge based electrical measurements on SiO 2 /Si interface was permanent and even clearly visible from the back side of the wafer. RTPL intensity variations at and near the measurement sites remained, even after a forming gas anneal. As devices scale to smaller size and complexity of device structures increase, the importance of proper understanding and control of the dielectric/Si interface is increasing. Advanced metal-oxidesemiconductor (MOS) and metal-insulator-semiconductor (MIS) devices employ ultra thin dielectric gate layers. The physical dimensions are in the range of single digit to double digit nanometers. The effective oxide thickness (EOT) is significantly less than 10 nm. Pure SiO 2 or combinations of SiO 2 and SiN layers are typically used as gate dielectrics. Materials with high dielectric constant (high-k dielectrics) and metal gates are also frequently used, depending on chip design.Conventional interface characterization techniques, such as high resolution cross-sectional transmission electron microscopy (HRX-TEM), Auger electron spectroscopy (AES), secondary ion mass spectroscopy (SIMS), X-ray photoelectron spectroscopy (XPS) and noncontact electrical measurement tools (for example, I-V, C-V and carrier life-time measurements) are either destructive or invasive (including methods which are non-contact, but impact dielectric/Si interface quality).1-3 The purpose of all these characterization techniques is to gain useful insights into dielectric/Si in various dimensions or aspects. While the conventional characterization techniques provide very useful information on many properties of the dielectric/Si interface, they appear unable to provide additional clues to some puzzling dielectric/Si interface problems....