Visualization of Verilog Digital Systems Models

Jelemenska, Katarina; Nosal, Milan; Čičák, Pavel

doi:10.1007/978-1-4614-3558-7_69

Cited by 3 publications

(9 citation statements)

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“…For this purpose the VCD2XML module from [8] was used as an inspiration. The VCD files analysis is based on the defined grammar and the analyzed data are stored in the internal memory.…”

Section: B Simulation Results Visualizationmentioning

confidence: 99%

“…For example in [7] authors dealt with the visualization of digital systems described in VHDL. On the other hand, Verilog models visualization is supported in the tool discussed in [8] and SystemC models support is presented in [9]. As far as the authors' knowledge extends none of the academic solutions supports more than two HDLs and the commercial solutions are highly complex to be appropriate for learning process.…”

Section: Related Workmentioning

confidence: 99%

“…The solutions [7][8][9] have already been used in the educational process for several years so the feedback and experience from students was analyzed as well to specify the requirements for the new system. The key requirements include support for several HDLs (at least the basic three), the possibility to extend support to other languages, visualization of model structure based on hierarchical levels in a well-arranged form, model simulation with simulation results displayed within the structure.…”

Section: The Visualization Framework Designmentioning

confidence: 99%

“…To design the HDL visualization framework the available solutions [1][2][3][4][5][6][7][8][9] have been thoroughly studied and tested. The solutions [7][8][9] have already been used in the educational process for several years so the feedback and experience from students was analyzed as well to specify the requirements for the new system.…”

Section: The Visualization Framework Designmentioning

confidence: 99%

“…In case of VHDL and Verilog the data extraction is based on source code analysis that is performed by separate parser for each language generated by the ANTLR parser generator [10]. The input grammars and parsers for the languages were inspired by [7] and [8]. The resulting modules VHDL2XML and Verilog2XML generate the XHDL data in several steps that had to respect the language specifics and therefore differ a bit based on the language.…”

Section: B Xhdl Data Extractionmentioning

confidence: 99%

See 4 more Smart Citations

Extensible framework for graphical representation of HDL models and Simulation Results

et al. 2013

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Digital systems models complexity requires often representation of their structure in graphical form. Also the simulation results of the models are often very extensive and for their effective browsing the proper representation is needed. We have proposed the methods for visualization of the digital systems models structure as well as their simulation outputs. The methods were designed to support the three most popular hardware description languages (HDLs) -VHDL, Verilog, and SystemC. For each language the algorithms were developed for transformation of model structure and simulation results into the common output forms that can be stored in common file formats for all the languages. To verify the solution all the methods were integrated into one system allowing to browse connections between modules on each level of model hierarchy. The simulation results can be displayed in the traditional waveform style, however the values of ports and signals at a particular time can be displayed directly in the visualized structure as well.

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“…For this purpose the VCD2XML module from [8] was used as an inspiration. The VCD files analysis is based on the defined grammar and the analyzed data are stored in the internal memory.…”

Section: B Simulation Results Visualizationmentioning

confidence: 99%