ViTaL: Verifying Trojan-Free Physical Layouts through Hardware Reverse Engineering

Abstract

The semiconductor industry is heavily relying on outsourcing of design, fabrication, and testing to third parties. The threat of possibly malicious actors in this ramified supply-chain poses a risk for the integrity of integrated circuits (ICs) and hardware Trojans (HTs) are a heavily discussed topic in academia and the industry. A variety of pre- and post-silicon HT prevention and detection techniques has been suggested in prior works. Hardware reverse engineering has the potential to detect potential modification in physical layouts. Yet, there is no model to qualitatively and quantitatively rate the complex and expensive reverse engineering (RE) process addressing its inherent process aberrations and consequently provide a tool for layout verification. The ViTaL framework introduces a statistical validation technique, based on physical layout verification through RE and considers all potential sources of errors. The golden-model based framework is technology-agnostic, scaleable, and user input is optional. For the first time, results of fine pitch metallization layers of a CMOS 40nm process node IC are presented quantitatively and the limitations and possibilities are discussed.<br>

Layout-Only Hardware Trojans: Attack Vectors and a Non-Golden Model Reverse Engineering-Based Counterstrategy

“…The probing is performed from the back-side of the die and does not necessarily require a golden chip but at least a golden layout to compare against. Destructive RE through delayering and full layout extraction through scanning electron microscopy is a viable way [14], [15] to detect layout HTs. It provides the ability to check a device in-depth and detect even tiny changes such as single wires or contact modifications.…”