Viterbi Accelerator for Embedded Processor Datapaths

Abstract

We present a novel architecture for a lightweight Viterbi accelerator that can be tightly integrated inside an embedded processor datapath. We investigate the accelerator's impact on processor performance by using the EEMBC Viterbi benchmark and the in-house Viterbi Branch Metric kernel. Our evaluation based on the EEMBC benchmark shows that an accelerated 65-nm 2.7-ns processor datapath is 20% larger but 90% more cycle efficient than a datapath lacking the Viterbi accelerator, leading to an 87% overall energy reduction and a data throughput of 3.52 Mbit/s.

FlexCore: Implementing an exposed datapath processor

“…An exposed datapath offers an interesting compromise solution using a mix of hardware acceleration-in a lightweight, memory-limited acceleratorand software execution-in the general-purpose portion of the datapath. To address acceleration of more complex algorithms, we recently described a Viterbi accelerator [21]. To complement the view of the previous two accelerator descriptions, we leave out all implementation details and instead focus on datapath integration and overall application execution.…”

“…The evaluation showed that by integrating the Viterbi accelerator, the datapath becomes 20% larger, which directly impacts power dissipation (a 38% increase). However, thanks to the improved performance, the reduced execution time (90% for the total benchmark or 99% for the benchmark kernel) yields an 87% energy reduction for the whole benchmark [21].…”

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

“…[4][5][6][7][8]). Besides power consumption, researches have been done on speed performance [9] and area efficiency (e.g. [10][11][12][13][14]).…”