VLIW instruction scheduling for minimal power variation

Abstract

The focus of this paper is on the minimization of the variation in power consumed by a VLIW processor during the execution of a target program through instruction scheduling. The problem is formulated as a mixed-integer program (MIP) and a problem-specific branch-and-bound algorithm has been developed to solve it more efficiently than generic MIP solvers. Simulation results based on the TMS320C6711 VLIW digital signal processor using benchmarks from Mediabench and Trimaran showed that over 40% average reduction in power variation can be achieved without sacrificing execution speed of these benchmarks. Computational requirements and convergence rates of our algorithm are also analyzed.Extension of conference paper [Xiao and Lai 2004]. The mixed-integer program in this paper makes use of a substantially improved set of constraints. The lower bound estimation of the branch-andbound algorithm has also been improved. The experimental results are, therefore, completely new.

Integrated energy-aware cyclic and acyclic scheduling for clustered VLIW processors

“…A comparison of various acyclic performance and energy aware instruction scheduling algorithms for a superscalar processor are presented in [25]. Xiao [26], proposes a branch-bound algorithm for a MILP formulation to minimize power variations for scheduling in VLIW processors. Nagpal [27], proposes an acyclic instruction scheduling algorithm for VLIW and clustered VLIW to reduce leakage energy of FUs.…”