VLSI architecture of dynamically reconfigurable hardware-based cipher

Abstract

This paper describes a 64-bit block, 128-bit key, dynamically reconfigurable hardware-based cipher, called Chameleon, in which two 32-cell, 8-context dynamically reconfigurable hardware units are employed to generate new subkeys for each of the 16 iterations in the encryptioddecryption process. The proposed architecture has been implemented by the 0.6 p m CMOS 3LM technology, using 65.6K transistors and attaining a maximum throughput of 3 17.5 Mbps. The new approach demonstrates distinctive features of enhanced complexity and flexibility dedicatedly for embedded encryptioddecryption applications in the mobile computing.