VLSI architecture of lossless ECG compression design based on fuzzy decision and optimisation method for wearable devices

Chen, Shih-Lun; Tuan, Min-Chun; Chi, Tsun-Kuang; Lin, Tsu-Wei

doi:10.1049/el.2015.2202

Cited by 26 publications

(3 citation statements)

References 7 publications

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“…Combining predictor with entropy coding algorithms makes the bit compression ratios vary between almost 48% and 58% [46][47][48][49] as shown in Table 3. Combining fuzzy optimization and Huffman region coding offers a BCR of 64.7% [50]. Nonetheless, adaptive trending predictor with modified Huffman and GR coding offers a BCR of 62.5% [51].…”

Section: Ecg Data Compression Methods' State Of the Artmentioning

confidence: 99%

Event-Driven ECG Sensor in Healthcare Devices for Data Transfer Optimization

Ben-Romdhane

Maalej

Tlili³

et al. 2020

Arab J Sci Eng

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The long-term monitoring of cardiovascular signs requires a wearable and connected electrocardiogram (ECG) healthcare device. It increases user's comfort and diagnosis quality of chronic cardiac and/or high-risk patients. This paper covers the enormous data to be transmitted from the ECG device to the physician's, namely the cardiologist's, control unit. Existent ECG devices uniformly sample analog signals and convert them to digital samples which are compressed before data transmission. However, event-driven sampling simultaneously compresses and samples. Therefore, this paper quantitatively compares successive approximation register analog-to-digital converter (SAR ADC) with discrete wavelet transform (DWT) compression and level-crossing analog-to-digital converter (LC-ADC). Evaluation metrics are the percent root-mean-square difference (PRD), bit compression ratio (BCR) and data length in bits. When a 12-bit reconstruction is operated on the outputs of an 8-bit LC-ADC with 12-bit and 10-kHz reference counter, the BCR is equal to 80% for 75% of test ECG signals. That is better than the 71.87% BCR of the 12-bit 1-kHz SAR ADC with DWT compression. The modeled LC-ADC guarantees a signal quality in terms of PRD comparable to the PRD of the SAR ADC with DWT compression. The data length in bits of the LC-ADC is lower than the data length in bits of the SAR ADC with more than 14-bit resolution with DWT compression for 82% of the test ECG signals. However, for lower resolutions, to obtain lower power consumption for radiofrequency transmission, a better alternative remains the SAR ADC with DWT compression.

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Section: Ecg Data Compression Methods' State Of the Artmentioning

confidence: 99%

Event-Driven ECG Sensor in Healthcare Devices for Data Transfer Optimization

Ben-Romdhane

Maalej

Tlili³

et al. 2020

Arab J Sci Eng

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“…Heart diseases are on the rise as a result of industrialization. The difficulty of transportation, as well as the scarcity of cardiologists in several areas, has increased the demand for telehealth and computerized ECG analysis [ 4 ]. Few applications in wearable technology healthcare are shown in Figure 1 .…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable Architectures with High-Frequency Noise Suppression for Wearable ECG Devices

Jerard

Thilagaraj

Pandiaraj

et al. 2021

Journal of Healthcare Engineering

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Recent advances in electronics and microelectronics have aided the development of low-cost devices that are widely used as well-being or preventive monitoring devices by many people. Remote health monitoring, which includes wearable sensors, actuators, and modern communication and information systems, offers effective programs that allow people to live peacefully in their own homes while also being protected in some way. High-frequency noise, power-line interface, and baseline drift are prevalent during the data-acquisition system of an ECG signal, and they can limit signal understanding. They (noises) must be isolated in order to provide an appropriate diagnostic of the patient. When removing high-frequency components (noise) from an ECG signal with an FIR filter, the critical path delay increases considerably as the filter's duration increases. To reduce high-frequency noise, simple moving average filters with pipelining and look-ahead transformation techniques are extensively used in this study. With the use of pipelining and look-ahead techniques, the only objective is to increase the clock speed of the designs. The moving average filters (conventional and proposed) were created on an Altera Cyclone IV FPGA EP4CE115F29C7 chip using the Quartus II software v13.1 tool. Finally, performance metrics such logic elements, clock speed, and power consumption were compared and studied thoroughly. The recursive pipelined 8-tap MA filter with look-ahead approach outperforms the other designs (685.48 MHz) in this investigation.

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“…Some low-hardware costs and low-power consumption designs are also developed in another work. One lossless algorithm using fuzzy-based PSO prediction and Huffman region entropy coding was described in [ 4 ], and the power consumption and hardware cost was reduced more effectively with system-on-chip (SoC) in wireless ECG sensors devices proposed in [ 5 ] than in previous lossless research [ 2 , 3 ].…”

Section: Introductionmentioning

confidence: 99%

Adaptive Integration of the Compressed Algorithm of CS and NPC for the ECG Signal Compressed Algorithm in VLSI Implementation

Tseng

Chen

2017

Sensors

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Compressed sensing (CS) is a promising approach to the compression and reconstruction of electrocardiogram (ECG) signals. It has been shown that following reconstruction, most of the changes between the original and reconstructed signals are distributed in the Q, R, and S waves (QRS) region. Furthermore, any increase in the compression ratio tends to increase the magnitude of the change. This paper presents a novel approach integrating the near-precise compressed (NPC) and CS algorithms. The simulation results presented notable improvements in signal-to-noise ratio (SNR) and compression ratio (CR). The efficacy of this approach was verified by fabricating a highly efficient low-cost chip using the Taiwan Semiconductor Manufacturing Company’s (TSMC) 0.18-μm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The proposed core has an operating frequency of 60 MHz and gate counts of 2.69 K.

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VLSI architecture of lossless ECG compression design based on fuzzy decision and optimisation method for wearable devices

Cited by 26 publications

References 7 publications

Event-Driven ECG Sensor in Healthcare Devices for Data Transfer Optimization

Event-Driven ECG Sensor in Healthcare Devices for Data Transfer Optimization

Reconfigurable Architectures with High-Frequency Noise Suppression for Wearable ECG Devices

Adaptive Integration of the Compressed Algorithm of CS and NPC for the ECG Signal Compressed Algorithm in VLSI Implementation

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