VLSI Architectures for Digital Video Signal Processing

Pirsch, P.

doi:10.1007/978-1-4615-3506-5_3

Cited by 25 publications

(32 citation statements)

References 9 publications

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“…We define the complexity of these DoA estimation algorithms in terms of basic operations [22], that is, additions and subtractions, multiplications, and divisions, and refer to them as ADD, MUL, and DIV, respectively. In the APPR algorithm case, part of the calculations can be calculated offline and stored into the LUT, in which case they do not need to be calculated in real time.…”

Section: Computational Complexity Analysismentioning

confidence: 99%

Experimental Results of Novel DoA Estimation Algorithms for Compact Reconfigurable Antennas

Paaso¹,

Hakkarainen

Gulati

et al. 2017

International Journal of Antennas and Propagation

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Reconfigurable antenna systems have gained much attention for potential use in the next generation wireless systems. However, conventional direction-of-arrival (DoA) estimation algorithms for antenna arrays cannot be used directly in reconfigurable antennas due to different design of the antennas. In this paper, we present an adjacent pattern power ratio (APPR) algorithm for twoport composite right/left-handed (CRLH) reconfigurable leaky-wave antennas (LWAs). Additionally, we compare the performances of the APPR algorithm and LWA-based MUSIC algorithms. We study how the computational complexity and the performance of the algorithms depend on number of selected radiation patterns. In addition, we evaluate the performance of the APPR and MUSIC algorithms with numerical simulations as well as with real world indoor measurements having both line-of-sight and non-line-ofsight components. Our performance evaluations show that the DoA estimates are in a considerably good agreement with the real DoAs, especially with the APPR algorithm. In summary, the APPR and MUSIC algorithms for DoA estimation along with the planar and compact LWA layout can be a valuable solution to enhance the performance of the wireless communication in the next generation systems.

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Section: Computational Complexity Analysismentioning

confidence: 99%

Experimental Results of Novel DoA Estimation Algorithms for Compact Reconfigurable Antennas

Paaso¹,

Hakkarainen

Gulati

et al. 2017

International Journal of Antennas and Propagation

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“…Iterative multipliers with radix-4 and radix-8 based on the Modified Booth's Recoding (MBR) algorithm are most commonly used in modem hardware design due to the low area requirement, low energy consumption and high throughput [9], [11]. In radix-4 MBR, sequential 3-bit segments of a 2's complement number are converted into the digit set { +2, +1, 0 }.…”

Section: Real-time Csd Multiplier Structurementioning

confidence: 99%

“…As in Booth recoding, the CSD representation [11] is a radix-2 number system using the digit set {1, 0, 1} with the "canonical" property that no two consecutive bits in the CSD number are nonzero. This representation replaces the additions arising from a string of ones in a binary number with a single subtraction, so that the "shift-and-add" algorithm becomes "shift-and-add/subtract".…”

Section: Introductionmentioning

confidence: 99%

Iterative Radix-8 Multiplier Structure Based on a Novel Real-time CSD Recoding

Wang

DeBrunner

Havlicek

et al. 2007

2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers

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Real-time implementation of many digital signal processing (DSP) algorithms and multimedia applications is performance limited by the available speed, energy efficiency, and area requirement of multiplication. This is exacerbated in handheld multimedia devices due to the small size and limited battery lifetimes. In our previous work, we introduce a novel canonical signed digit (CSD) iterative multiplier structure in which the conversion from 2's complement to CSD representation is implicitly implemented in real-time. In this work, we further improve the iterative multiplier performance by introducing explicit radix-8 hardware support in which the multiplier is shifted by one octal digit in each iteration as opposed to only one or two bits. Thus, this new structure further reduces the power consumption while simultaneously increasing the computational bandwidth significantly with only a small sacrifice in area consumption. This new design also uses a bypass technique to further reduce the need for devices such as carry save adder (CSA) arrays and adder trees for partial product reduction operations. Therefore, the new structure introduced here greatly improves the multiplier throughput and energy efficiency. Moreover, the number of iterations required to complete a fixed length multiply is data dependent as a result of a novel variable shifting technique; hence there is no energy and time overhead expended for unnecessary iterations as observed in multipliers where the number of iterations is fixed. Our results show that this new iterative structure delivers significant performance improvements with respect to speed, area, and power consumption relative to previous iterative multiplier designs.

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“…These technologies offer the opportunity to integrate applications like video conferences, multimedia database access, video-on-demand, etc., on a single computer platform (e.g., workstation, PC). A key problem in this context is the handling of real-time video data [96] [108]. Typically, this leads to unacceptable storage and network-bandwidth requirements.…”

Section: V'uteo Compression -An Example Of a High Performance Es Designmentioning

confidence: 99%

Embedded system design

Camposano

Wilberg²

1996

Des Autom Embed Syst

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In the past decade the main engine of electronic design automation has been the widespread application of ASICs (Application Specific Integrated Circuits). Present technology supports complete systems on a chip, most often used as so-called embedded systems in an increasing number of applications. Embedded systems pose new design challenges which we believe will be the driving forces of design automation in the years to come. These include the design of electronic systems hardware, embedded software and hardware / software codesign. This paper explores the novel technical challenges in embedded system design and presents experiences and results of the work in this area using the CASTLE system. CASTLE supports the design of complex embedded systems and the design of the required tools. It provides a central design representation. Verilog, VHDL and C/C++ frontends. Hardware generation in VHDL and BLIF, a retargetable compiler back-end and several analysis and visualization tools. Two design examples, video compression and a diesel injection control, illustrate the presented concepts

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VLSI Architectures for Digital Video Signal Processing

Cited by 25 publications

References 9 publications

Experimental Results of Novel DoA Estimation Algorithms for Compact Reconfigurable Antennas

Experimental Results of Novel DoA Estimation Algorithms for Compact Reconfigurable Antennas

Iterative Radix-8 Multiplier Structure Based on a Novel Real-time CSD Recoding

Embedded system design

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