VLSI Architectures of a Wiener Filter for Video Coding

Abstract

In the modern age, the use of video has become fundamental in communication and this has led to its use through an increasing number of devices. The higher resolution required for images and videos leads to more memory space and more efficient data compression, obtained by improving video coding techniques. For this reason, the Alliance for Open Media (AOMedia) developed a new open-source and royalty-free codec, named AOMedia Video 1 (AV1). This work focuses on the Wiener filter, a specific loop restoration tool of the AV1 video coding format, which features a significant amount of computational complexity. A new hardware architecture implementing the separable symmetric normalized Wiener filter is presented. Furthermore, the paper details possible optimizations starting from the basic architecture. These optimizations allow the Wiener filter to achieve a 100× reduction in processing time, compared to existing works, and 5× improvement in megasamples per second.

High-Throughput Hardware Design for the AV1 Decoder Switchable Loop Restoration Filters

“…The first work was presented in [33], but as previously discussed, they focused on the encoder side and focused on UMC 45nm technology. The synthesis results reported an area of 1,988,927.2 µm 2 , when our solution used only 35,167.1 µm 2 .…”

“…The synthesis results reported an area of 1,988,927.2 µm 2 , when our solution used only 35,167.1 µm 2 . The work in [33], process FHD (1920x1080) videos at 42.4 fps when running at 75.24 MHz and consuming 12.8 mW. For the same resolution, but with a little smaller frame rate of 30 fps, our SSNWF architecture must run at only 30 MHz, consuming 8.25 mW.…”

“…For the same resolution, but with a little smaller frame rate of 30 fps, our SSNWF architecture must run at only 30 MHz, consuming 8.25 mW. Then, the work in [33], uses 56.5 times more area, requires 2.5 times higher frequency and consumes 1.6 times more power than our solution to process the same video resolution.…”

“…Six works have been published focusing on the In-loop filtering stage, and five of them were developed in our previous work: [28] and [29] are solutions targeting the CDEF, [30] target the DBF filters, and [31] and [32] target the SLRF filters, respectively for the SSNWF and the DSGF. The sixth work presents a hardware design for the SSNWF targeting the encoder side [33].…”