VLSI CAD for emerging nanolithography

Pan, David Z.; Gao, Jhih-Rong; Yu, Bei

doi:10.1109/vlsi-dat.2012.6212644

Cited by 2 publications

(1 citation statement)

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“…The introduction of MP technology gave us the capability to successfully image designs at 20 nm and below. However, while the actual MP process occurs in the foundry, some MP solutions impose new layout, physical verification, and debugging requirements on the design side [1]. All MP technologies require new software tools in order to incorporate their specific constraints in the design, layout, and verification stages.…”

Section: Introductionmentioning

confidence: 99%

Decomposition technologies for advanced nodes

Pikus¹

2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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We present an overview of several techniques that are used when the layout pitch and feature size become significantly smaller than the minimum resolution of the lithographic process. These technologies, known collectively as multi-patterning (MP) share the common approach: a single layer is decomposed into two or more masks and printed in multiple stages. However, a great variety of approaches exists when it comes to details. There are several different ways to combine multiple masks into one final layer, each with its own advantages and drawbacks. The choice of multi-patterning technology is closely connected with the process technology, of course, but it turns out to have major implications on the entire IC design flow. We will review the major types of multi-patterning technologies, their impact on the lithographic process, yield, and design flow, and the requirements they impose on designers and on the EDA tools.

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Section: Introductionmentioning

confidence: 99%