VLSI cell placement techniques

Shahookar, K.; Mazumder, Pinaki

doi:10.1145/103724.103725

Cited by 241 publications

(102 citation statements)

References 36 publications

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“…Nine different test-cases were considered from ami standard cell library. These test cases were mapped over 0.18 micron, 5 metal layer standard cell library [7]. In Algorithm-II [2] layout width was constrained not to exceed 1.25 times the average row width.…”

Section: Resultsmentioning

confidence: 99%

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MultiObjective Optimization of Standard Cell Placement using Memetic Algorithm

Bunglowala¹,

Singhi²,

Verma³

2011

IJCA

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Beyond the optimization of single parameter (usually the wire-length) in Standard Cell Placement (SCP), focus in the present work is laid on the optimization of speed, power, and the wire length. As discussed in our previous work of hybrid algorithms for single objective optimization of SCP the main advantage of hybridization is the improvement in convergence speed to Pareto front although it leads to increase in computation time per generation. Memetic Algorithm (MA) is a hybrid of Genetic Algorithm (GA) & Local search (LS) wherein we need to strike a right balance of the two for optimum solution. In this paper we work on our previous GA based multi-objective SCP algorithm [2] for simultaneous optimization of power, speed and wire length while maintaining the layout width as constant by choosing initial population to be alleles of high fitness value and apply proper local search to all the members of initial population. Further we compare the results with previously established GA based algorithm by applying the two on ami20, ami33 and ami120 cell library instances. The Memetic algorithm is found to give better results with 10% improvement in wire-length, 7.5% lesser delay and power consumption reduction by nearly 6%.

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Section: Resultsmentioning

confidence: 99%

“…These problems cannot be solved in polynomial time. Trying to evaluate every possible placement to determine the best one takes time proportional to the factorial of number of cells [7]. Therefore heuristic algorithms are used to search through a large number of candidate placement configurations.…”

Section: Introductionmentioning

confidence: 99%

MultiObjective Optimization of Standard Cell Placement using Memetic Algorithm

Bunglowala¹,

Singhi²,

Verma³

2011

IJCA

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“…Many research works have been devoted to automatic floorplanning of digital circuits, we refer the reader to [9] for a comprehensive review of these techniques. The focus of the paper we present here is on ILP floorplanning for reconfigurable hardware.…”

Section: Related Workmentioning

confidence: 99%

Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

Smith

Constantinides

Cheung

2008

IEEE Trans. VLSI Syst.

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Abstract-This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMs, and LUT-based logic, in order to maximise the performance of a set of DSP benchmark applications, given a fixed silicon budget. A mathematical programming framework is introduced, along with a set of heuristics, capable of providing upper-bounds on the achievable reconfigurable-to-fixed-logic performance ratio. Moreover, we use linear-programming bounding procedures from the operations research community to provide lower-bounds on the same quantity. Our results provide, for the first time, quantifications of the optimal performance/area-enhancing capability of multipliers and RAM blocks within a system context. The approach detailed provides a formal mechanism to explore future technology nodes.

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“…Among many available placement algorithms, we adopted a min-cut based placement algorithm that is reported having reasonable computation time and yet generating effective placements in [18]. Min-cut placement algorithm repeatedly divides the given resources into several spatial partitions and distributes operations while minimizing the number of nets cut generated by the partitions.…”

Section: Placement and Routingmentioning

confidence: 99%

Configuration Sharing to Reduce Reconfiguration Overhead Using Static Partial Reconfiguration

Jung

Kim

2008

IEICE Transactions on Information and Systems

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SUMMARY Reconfigurable architectures are one of the most promising solutions satisfying both performance and flexibility. However, reconfiguration overhead in those architectures makes them inappropriate for repetitive reconfigurations. In this paper, we introduce a configuration sharing technique to reduce reconfiguration overhead between similar applications using static partial reconfiguration. Compared to the traditional resource sharing that configures multiple temporal partitions simultaneously and employs a time-multiplexing technique, the proposed configuration sharing reconfigures a device incrementally as an application changes and requires a backend adaptation to reuse configurations between applications. Adopting a data-flow intermediate representation, our compiler framework extends a min-cut placer and a negotiation-based router to deal with the configuration sharing. The results report that the framework could reduce 20% of configuration time at the expense of 1.9% of computation time on average.

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VLSI cell placement techniques

Cited by 241 publications

References 36 publications

MultiObjective Optimization of Standard Cell Placement using Memetic Algorithm

MultiObjective Optimization of Standard Cell Placement using Memetic Algorithm

Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

Configuration Sharing to Reduce Reconfiguration Overhead Using Static Partial Reconfiguration

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