VLSI design of efficient FIR filters using Vedic Mathematics and Ripple Carry Adder

Samyuktha, Sripathi; Chaitanya, D. L.

doi:10.1016/j.matpr.2020.08.391

Cited by 10 publications

(14 citation statements)

References 9 publications

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“…The proposed design is successfully implemented using SGP along Intel(R), Core(TM) 2 Duo CPU T6600 @ 3.2 GHz environments and targeted family Spartan3 with device XC6slx9 and package TQG144 utilizes VPL at Xilinx ISE 14.5 design tools. The performance of the proposed APM‐CDF‐ESDCSA‐TOSAM filter is compared with the existing filters, such as DF‐VBSTA‐MTM, 25 DF‐RCA‐VM, 27 and DF‐VL‐CSKA‐BM, 32 respectively.…”

Section: Resultsmentioning

confidence: 99%

“…Samyuktha and Chaitanya 27 have presented VLSI design of efficient FIR filters using Vedic Mathematics and ripple carry adder. Ripple carry adder (RCA) was used and this adder was used to achieve lesser intricacy.…”

Section: Literature Surveymentioning

confidence: 99%

“…And also, decreased energy/power consumption and delay, but increased the speed of the system. The designed APM‐CDF‐ESDCSA‐TOSAM filter consumes less power, area and the speed is increased and it is applicable in the image processing application for providing filtered high quality images 25 The proposed APM‐CDF‐ESDCSA‐TOSAM filters is designed and executed in Verilog programming language and simulated on Xilinx ISE 14.5 designing tool are observed through the overall area, power, delay, and speed. The experimental performance of the proposed DF‐ESDCSA‐TOSAM filter is calculated area, power, delay and speed and the efficiency of the proposed APM‐CDF‐ESDCSA‐TOSAM filter is compared with the existing filters, such as DF‐VBSTA‐MTM, 25 DF‐SQRTCSLA‐BM, 5 DF‐RCA‐VM, 27 DF‐VL‐CSKA‐BM, 28 DF‐CSLA, 29 DF‐ESDCSA, 24 respectively. The proposed APM‐CDF‐ESDCSA‐TOSAM filter is used in the image processing applications. The APM‐CDF‐ESDCSA‐TOSAM filter is simulated using MATLAB.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application

Mahendran¹,

Kavitha

Radhika³

et al. 2023

Concurrency and Computation

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A design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation based scalable rounding approximate multiplier (APM-CDF-ESDCSA-TOSAM) is proposed in this article for image processing application. The proposed ESDCSA-TOSAM is used to speed up the filter design with less area and less power consumption. In the existing designs, a carry select adder was used that was a rapid binary adders, even though, it consumes maximal area and power. For that reason, lower power, area efficient with higher speed eminent speed dual carry select adder (ESDCSA) is used in this work. The proposed ESDCSA is a fastest binary adder, which consumes less power and area. To design the ESDCSA, three blocks are used: half sum with carry generator (HSCG), final carry generator (FCG), final sum generator (FSG), these are reducing the power and area. TOSAM is used to reduce more partial products by truncating each input operands depending on its leading one-bit position.The proposed filter is designed on Xilinx ISE 14.5 design tools. The experimental performance of the proposed filter attains lower delay 59.61%,

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Section: Resultsmentioning

confidence: 99%

Section: Literature Surveymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application

Mahendran¹,

Kavitha

Radhika³

et al. 2023

Concurrency and Computation

View full text Add to dashboard Cite

show abstract

“…Problem arose that compressor produce only approximated value, not accurate value which affects the filtering performance. Samyuktha S and Chaitanya et al [14] DL proposed an effective FIR filter using the multiplication principle of vedic mathematics and Ripple carry adder. Frequently, Single Constant Multiplication (SCM) and Multiple Constant Multi plication (MCM) were used in FIR implementation.…”

Section: Literature Review Pramod Patali and Shahana Thottathikkulammentioning

confidence: 99%

“…Even though conflicts were solved cross-checking of the results was difficult and also the identification of vedic mathematic classification was a problem. Shinwoong Park et al [13][14][15] developed an analog FIR filter system specially designed for full bandwidth utilization in communication by using split capacitive DAC's. Split DAC's acted as multiplier co-efficient that were controlled by 7-bit codes to provide high linearity over the full frequency range.…”

Section: Literature Review Pramod Patali and Shahana Thottathikkulammentioning

confidence: 99%

Array Multiplier and CIA based FIR Filter for DSP applications

B.N¹,

H.G²

2021

IRJASH

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In Field Programmable Gate Array (FPGA) platform, Finite Impulse Response (FIR) filter is one of the important applications in the context of Digital Signal Processing (DSP). The traditional FIR is designed using a number of the adders, multipliers which enlarge the area of the filter architecture. Generally, the multiplier and adder are required to design the FIR filter. In this research, Array Multiplier (AM) is used in the Processing Element (PE) for multiply the filter inputs with coefficients. This research employs the Carry Increment Adder (CIA) in the accumulator for the adding output of the PE. The proposed method is named as AM-CIA-FIR filter. Due to the usage of AM and CIA adder, the hardware utilization of the proposed work is improved. The AM-CIA-FIR filter is implemented in Xilinx ISE software by using Verilog code on different Virtex devices in terms of Virtex-4, Virtex-5, and Virtex-6. This experiment results showed that AM-CIA-FIR filter has reduced 14.01 % of the FPGA utilization compared to the PSA-FIR filter design.

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Design of recustomize finite impulse response filter using truncation based scalable rounding approximate multiplier and error reduced carry prediction approximate adder for image processing application

Senthilkumar¹,

Pandi

Sripriya

et al. 2023

Concurrency and Computation

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Summary Recustomize finite impulse response (RFIR) filter is designed to achieve lesser power consume, cost, area, and higher speed of system operation. This is used to remove the noises from the image and signal. Previously, several filters were designed for removing noises, but that filters consume more area, power, cost, and delay and did not provide accurate results and the error rate was increased. To overcome these issues, this work is proposed. In this work, the Recustomize finite impulse response (RFIR) filter is designed using truncation‐based scalable rounding approximate multiplier (TOSAM) and error reduced carry prediction approximate adder (ERCPAA) for image processing application. Here, TOSAM‐ERCPAA is used to speed up the filter design with less area and less power consumption. The proposed ERCPAA adder is divided into three blocks, such as carry prediction logic, approximate full adder cells array, constant truncation along error lessening logic, which can reduce the power and area. The proposed RFIR‐ TOSAM‐ERCPAA filter is designed and executed in Verilog programming language and the simulation is done in Xilinx ISE 14.5 design tools.

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VLSI design of efficient FIR filters using Vedic Mathematics and Ripple Carry Adder

Cited by 10 publications

References 9 publications

Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application

Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application

Array Multiplier and CIA based FIR Filter for DSP applications

Design of recustomize finite impulse response filter using truncation based scalable rounding approximate multiplier and error reduced carry prediction approximate adder for image processing application

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