VLSI design of low power SRAM architectures for FPGAs

Kaushik, Chakka Sri Harsha; Vanjarlapati, Rajiv Reddy; Krishna, Varada Murali; Gautam, Tadavarthi; Elamaran, V.

doi:10.1109/icgccee.2014.6922244

Cited by 12 publications

(6 citation statements)

References 8 publications

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“…The below tabulation justifies all the mentioned statements on power consumption comparisons. Table 3 presents an information on layout areas of various designs presented here and compared with the previous studies (Kaushik et al, 2014). The proposed SRAM cells are having the similar performance compared with the previous studies.…”

Section: Resultsmentioning

confidence: 51%

“…The results are available in Table 2. The present proposed method results are compared with the previous studies (Kaushik et al, 2014). It is apparent that the proposed 6-T SRAM cells are good with low power dissipation for the 70, 120 and 180 nm technologies.…”

Section: Resultsmentioning

confidence: 71%

“…Figure 1 shows a 6T SRAM cell. The two transistors placed outside inverter circuits are called access transistors as they control the access of data to the cell during read and write operations (Kaushik et al, 2014;Athe and Dasgupta, 2009;Yu et al, 2010).…”

Section: Methodsmentioning

confidence: 99%

“…Res., 8 (4): 466-477, 2015 Fig. 15: Power dissipation result with a proposed voting circuit for 120 nm process compared with the studies made by Kaushik et al (2014). The proposed TMR with SRAM cell offer a better layout area at the cost of power dissipation compared with the approach made by Kshirsagar and Patrikar (2009).…”

mentioning

confidence: 99%

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CMOS VLSI Design of Low Power SRAM Cell Architectures with New TMR: A Layout Approach

Elamaran¹,

Upadhyay²

2015

Asian J. of Scientific Research

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Rapid increase in technology for faster and smarter innovations that smoothens the needs of humans resulting in use of super tech gadgets, which use memory, such as, RAM. To meet the increasing demands, the size is getting reduced and the need to save power arises which reduces the equipment for cooling processes and maintenance. The SRAM cells with lower power dissipation and proper read and write stability is required. This study deals with the design of SRAM cells with low power dissipation in comparison with the conventional SRAM cell design. The SRAM cell design ranges from 3-14T depending on the importance of the application. Here we choose the 6T SRAM cell. The elementary structure uses pass transistor and CMOS, while the proposed SRAM consists of Transmission gates, CMOS, Pseudo-NMOS. This proposed model is compared with two other models of varied 6T SRAM cell. This study also exemplify with the new Triple Modular Redundancy (TMR) techniques with SRAM cell architecture and the layout area with power dissipation results are compared with the existing voting mechanism in 50, 70 90 and 120 nm foundry fabrication process technologies. It is apparent that the proposed voting circuit produces less area at the cost of power dissipation.

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Section: Resultsmentioning

confidence: 51%

Section: Resultsmentioning

confidence: 71%

Section: Methodsmentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

CMOS VLSI Design of Low Power SRAM Cell Architectures with New TMR: A Layout Approach

Elamaran¹,

Upadhyay²

2015

Asian J. of Scientific Research

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“…1 and 2. The Cache Memory Design for Single-Bit Architecture includes WDC, STSRAM, and other sense amplifiers, including voltage differential and current latch sense amplifiers [11,12]. ____________________ *Corresponding author; Assistant Professor, Department of Mechanical Engineering, SR Institute of Management and Technology, Lucknow, Uttar Pradesh, India (E-mail: sriabhi1991@gmail.com) **Assistant Professor, Department of Mechanical Engineering, Bansal Institute of Science and Technology, Bhopal, Madhya Pradesh, India (E-mail: shashanksaxena7oct@gmail.com) ***Director, DKT Technology Services Pvt.…”

Section: Single Bit Architecture Cache Memory Designmentioning

confidence: 99%