VLSI floorplanning with boundary constraints based on corner block list

Ma, Yuchun; Dong, Sheqin; Hong, Xianiong; Cai, Yici; Cheng, Chung‐Kuan; Gu, Jun

doi:10.1145/370155.370521

Cited by 37 publications

(18 citation statements)

References 9 publications

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“…BLK [4] BLK [5] BLK [6] BLK [7] BLK [8] BLK [9] BLK [10] BLK [11] BLK BLK [2] BLK [3] BLK [4] BLK [5] BLK [6] BLK [7] BLK [8] BLK [9] BLK [10] BLK [11] BLK …”

Section: Discussionmentioning

confidence: 99%

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Consistent floorplanning with super hierarchical constraints

Nakatake

Kubo

Kajitani

2001

Proceedings of the 2001 International Symposium on Physical Design

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Sequence-Pair based floorplanning has been revealed its limit of usefulness in VLSI physical design. Among reasons, the key issue is in its being non-hierarchical and indifferent to the preceding step of partitioning. This paper restructure the algorithm by the idea that the partition algorithm produces the constraint that is imposed on the sequence-pair data. The partition algorithm is the one based on the balancedbipartition that works hierarchically. Thus a new floorplan algorithm that is consistent with the hierarchical partition algorithm is constructed. This is enhanced to include other algorithms that are based on the binary search. Here, a clock-tree synthesis by H-tree is shown to be consistent. Experiments are given to show better achievements in length and wire-density.

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“…BLK [4] BLK [5] BLK [6] BLK [7] BLK [8] BLK [9] BLK [10] BLK [11] BLK BLK [2] BLK [3] BLK [4] BLK [5] BLK [6] BLK [7] BLK [8] BLK [9] BLK [10] BLK [11] BLK …”

Section: Discussionmentioning

confidence: 99%

“…This merit is by a trade-off to the structural generality. A new type floorplanning by Q-Sequence (QS) [10] or Corner-Block-List [11] is classified to the category of topological packing. However, what is to be stressed is that only the dimensions that affects the topology in the following stages are significant.…”

Section: Introductionmentioning

confidence: 99%

Consistent floorplanning with super hierarchical constraints

Nakatake

Kubo

Kajitani

2001

Proceedings of the 2001 International Symposium on Physical Design

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“…The representation should be able to traverse large search space in least computational time. The existing representations for non-slicing floorplans are Bounded Slicing Grid Structure (BSG) [19] [20], Corner Block List (CBL) [21], Corner Sequence (CS) [22], Sequence Pair (SP) [23] [24], B* Tree [25] [26], Transitive Closure Graph (TCG) [27] [28], Integer Coding [29], O Tree [30]. These representations can be compared based on solution space search and computational complexity as shown in Table 1.…”

Section: Representations For Non-slicing Floorplansmentioning

confidence: 99%

Early Layout Design Exploration in TSV-based 3D Integrated Circuits

Ahmed¹

2000

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Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage.The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% -12% compared to wirelength-aware cost function.ii The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance.Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and blocks, as well as nets-to-TSVs assignment to obtain floorplans with minimized coupling noise.We also suggested diagonal TSV arrangement for larger TSV pitch and nonuniform pitch arrangement for reducing worst TSV-to-TSV coupling, thereby minimizing the coupling noise in the interconnects.This thesis also focuses on more realistic evaluation and optimization of delay and power in TSV based 3D integrated circui...

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“…The floorplanners in [4,10,11] can handle pre-place constraint in which some modules are fixed in position. The paper [12][13][14] work on boundary constraint in which some modules are constrained to be placed along one of the four sides of the chip for I/O connection. The paper [15] generalizes the approach in [10] to handle range constraint in which some modules are restricted to be placed within some rectangular ranges.…”

Section: Introductionmentioning

confidence: 99%

Multi-bend bus driven floorplanning

Law

Young

2005

Proceedings of the 2005 International Symposium on Physical Design

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In this paper, the problem of bus-driven floorplanning is addressed. Given a set of blocks and bus specifications (the width of each bus and the blocks that the bus need to go through), we will generate a floorplan solution such that all the buses go through their blocks, with the area of the floorplan and the total area of the buses minimized. The approach proposed is based on a simulated annealing framework. Using the sequence pair representation, we derived and proved some necessary conditions for feasible buses, for which we allow 0-bend, one-bend, or two-bend. A checking will be performed to identify those buses that cannot be placed simultaneously. Finally, a solution will be generated giving the coordinates of the modules and the buses.

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VLSI floorplanning with boundary constraints based on corner block list

Cited by 37 publications

References 9 publications

Consistent floorplanning with super hierarchical constraints

Consistent floorplanning with super hierarchical constraints

Early Layout Design Exploration in TSV-based 3D Integrated Circuits

Multi-bend bus driven floorplanning

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