VLSI hardware design of QR-factorizer for a V-BLAST detector

Abstract

This paper presents a new, reduced complexity, architecture for the QR-factorizer for the V-BLAST detector. This architecture employs only two low complexity CORDIC processors for the QRfactorization. This results in a suitable alternative architecture for QR-factorization than the triangular systolic arrays. The implementation of the proposed architecture on the Altera Stratix FPGA device results in a very small critical path delay. This provides a platform for the fast matrix triangularization for applications requiring high data rates such as MIMO V-BLAST detectors.