VLSI implementation of an efficient MBIST architecture using RLFSR

Nisha, O. S. Jannath; Sankar, K. Siva

doi:10.1504/ijscc.2020.109076

Cited by 2 publications

(1 citation statement)

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“…Applying word-oriented transactions saves huge test time compared to applying bit-oriented transactions. The algorithm covers stuck at, transition, coupling, read disturb, and address decoder faults f) Modified March Y [53]: Number of operations per cell = 8N…”

Section: : Number Of Operations Per Cell = 22nmentioning

confidence: 99%

Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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Newer defects in memories arising from shrinking manufacturing technologies demand improved memory testing methodologies. The percentage of memories on chips continues to rise. With shrinking technologies (10 nm up to 1.8 nm), the structure of memories is becoming denser. Due to the dense structure and significant portion of a chip, the nanometer memories are highly susceptible to defects. High-frequency specifications, the complexity of internal connections, and the process variation due to newer manufacturing technology further increased the probability of the physical failure of memories to a great extent. Memories need to be defect-free for the chip to operate successfully. Therefore, testing embedded memories has become crucial and is taking significant test costs. Researchers have proposed multiple approaches considering these factors to test the nanometer memories. They include using new fault models, march algorithms, memory built-in self-test (MBIST) architectures, and validation strategies. This paper surveys the methodologies presented in recent times. It discusses the core principles used in them, along with benefits. Finally, it discusses key opens in each and offers the scope for future research.

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Section: : Number Of Operations Per Cell = 22nmentioning

confidence: 99%

Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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Synchronized Multi-Rate Test Pattern Generation Using Hybrid Twisted Ring Counter and LFSR for BIST Application

Priya

Sarada

2021

J. Phys.: Conf. Ser.

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This work presents a new approach for built-in test pattern generation (BIST) based on the variable rate clock-driven linear feedback shift register (LFSR) and twisted-ring counters (TRCs). The proposed technique operates on different operating clocks for generating deterministic test pattern sequence for the circuit under test (CUT). The test vectors generated by LFSR are transformed and reproduced with TRC results. The TRC design constitutes of only flip-flops, which be used as a potential alternative to improved seed storage and complex multi polynomial configurations in LFSR. Moreover, the control logic is simplified with synchronized multi-rate clock generation and can be easily extended for any test cubes among multiple CUTs. The randomness characteristics of LFSR are retained with improved memory efficiency and considerable complexity reduction. Experimental results validate the proposed test pattern generator (TPG) over existing well-known LFSRs models, and its randomness is proved with ISCAS benchmark circuits.

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VLSI implementation of an efficient MBIST architecture using RLFSR

Cited by 2 publications

References 0 publications

Testing nanometer memories: a review of architectures, applications, and challenges

Testing nanometer memories: a review of architectures, applications, and challenges

Synchronized Multi-Rate Test Pattern Generation Using Hybrid Twisted Ring Counter and LFSR for BIST Application

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