VLSI Implementation of High Performance Optimized Architecture for Video Coding Standards 

Abstract

This study presents a fast search algorithm and its Very Large Scale Integration (VLSI) design to implement an Enhanced Diamond Search (EDS) of Block-based Motion estimation for video compression systems. The proposed algorithm reduces the number of search points with a slight increase in average Sum-of-Absolute Difference (SAD) per pixel and significant reduction in Peak Signal-to-Noise Ratio (PSNR) than the Full search (FS). The speed improvement ratio is 11.26%. A novel Motion Estimation (ME) algorithm is proposed in this study that exhibits some properties with potential to facilitate optimized VLSI implementation and to achieve high performance for real video sequences. The main characteristic of this proposed architecture is possessing of only five processing elements (PE) that are used to calculate minimum SAD by using efficient comparators and compressors. Simulation results indicate that our proposed architecture employs low power and processes the video data with high speed than existing architectures without significant change in the video quality.