VLSI implementation of low power scan based testing

Ukey, Shashank; Rathkanthiwar, Shubhangi; Kakde, Sandeep

doi:10.1109/iccsp.2016.7754270

Cited by 8 publications

(4 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Tables 1 and 2 provides their classification based on the common principle being used. [9]- [13]. They block the functional output going to the combinational logic during test mode, thereby reducing redundant switching during shifting.…”

Section: Classificationmentioning

confidence: 99%

See 1 more Smart Citation

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

View full text Add to dashboard Cite

While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

show abstract

Section: Classificationmentioning

confidence: 99%

“…Figure 1. Scan cells with gated functional output during shifting, (a) cell with separate latches for functional and scan path [13] and (b) trimodal scan cell [11] The cell in [9] removes the slave part in a conventional scan cell. Also, its scan path sees two fewer inverters and one less transmission gate.…”

Section: Classificationmentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

View full text Add to dashboard Cite

show abstract

“…Design-For-Testability (DFT) has major importance in chip manufacturing to reduce the testing cost and time. The most popular DFT method for sequential circuits is the fully scanned design [37]. The basic structure of the scan is using the flip-flop with a 2 × 1 multiplexer.…”

Section: Design For Testabilitymentioning

confidence: 99%

Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Hamed

Lee

2021

Electronics

View full text Add to dashboard Cite

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

show abstract

“…Specifically, a methodology was designed for indigenous scan cell style for low-power scan with high efficiency with respect to power. This offers clarification for decreasing the complete mean power in set of two that is scan cell and combinational part at the time of capture and shift mode [19]. Error report was scaled for estimation of the errors that are called stuck-at range of visionary test sequences that is introduced by evading sequential error simulation [20].…”

mentioning

confidence: 99%

Fault simulation for design for testability inserted designs

Gowda

Jamuna²

2023

IJEECS

View full text Add to dashboard Cite

<p>Systematic design for testability (DFT) is a technique to enhance the testability of design so that it is further organized and self-regulating. The objective of systematic DFT is to enhance a circuit's operability and evidence. This can be performed in a variety of ways. The scan pattern method is the extremely predominant, and it modifies the design's internal sequential circuitry. In this manuscript, frequently used industry standard functional register-transfer level (RTL) designs are chosen. Structured DFT approach is adopted to do scan insertion and automatic test pattern generation (ATPG) to enhance the testability. Proposed methodology provides the controllability and observability for the clocks and reset used in chosen RTL designs by eliminating S rule and D rule violations by adding test logic. Also able to insert stuck at faults and achieve fault coverage of 97.78% and test coverage of 99.26% for DFT architecture for Wallace tree multiplier design, and found different classes of faults as testable and untestable faults and also performed fault simulation for the intended designs to detect fault from the created deterministic patterns.</p>

show abstract

VLSI implementation of low power scan based testing

Cited by 8 publications

References 10 publications

Developments in scan shift power reduction: a survey

Developments in scan shift power reduction: a survey

Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Fault simulation for design for testability inserted designs

Contact Info

Product

Resources

About