VLSI implementation of public-key encryption algorithms

Abstract

This paper describes some recently successful results i n the CMOS VLSI implementation of public-key data encryption algorithms. Architectural details, circuits, and prototype test results are presented for RSA encryption and multiplication in the finite field GF(2"). These designs emphasize high throughput and modularity. An asynchronous modulo multiplier i s described which permits a significant improvement in RSA encryption throughput relative to previously described synchronous implementations.

Hardware architectures for public key cryptography

“…Orton et al gave a nice collection of modular multiplication algorithms in [145]. They presented the implementation results of one of the algorithms which was most efficient according to their results.…”

Applied cryptography: Protocols, algorithms, and source code in C

“…Much has been written on the subject of hardware implementations of RSA [1314,1474,1456,1316,1485,874,1222,87,1410,1409,1343,998,367,1429,523,772]. Good survey articles are [258,872].…”

A design of a fast pipelined modular multiplier based on a diminished-radix algorithm

“…A chip developed by Orton, Peppard, and Tavares in 1986 (Queen's 86) uses an asynchronous pulse-timed adder [22]. The average length of the longest continuous carry propagation in a k-bit addition is within log2 k bits.…”

“…There are many variations on this theme [1], [7], [19], [22], [32], however, the number of bits that can be reduced in parallel is limited because the number of stored multiples of the modulus grows exponentially with the number of bits being reduced. There are many variations on this theme [1], [7], [19], [22], [32], however, the number of bits that can be reduced in parallel is limited because the number of stored multiples of the modulus grows exponentially with the number of bits being reduced.…”