VLSI implementation of the sphere decoding algorithm

Burg, Andreas; Wenk, M.; Zellweger, M.; Wegmueller, Marc Simon; Felber, N.; Fichtner, W.

doi:10.1109/esscir.2004.1356678

Cited by 31 publications

(25 citation statements)

References 7 publications

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“…Compared to a previously presented implementation [8], it only requires a third of the area and achieves a 50% higher clock rate. Also, fewer iterations are required for the decoding due to the complexity reduction by the ∞ -norm approximation and other minor optimizations.…”

Section: Asic Implementation Resultsmentioning

confidence: 98%

“…However, it is crucial to realize that only the first two ideas described above are actually prerequisites for the tremendous complexity savings of the SD algorithm over a brute force search. In fact, sphere decoding is applicable to arbitrary sets of constellation points, in particular to complex lattices [7], [8]. In this case, the PED computation becomes…”

Section: Admissible Intervalsmentioning

confidence: 99%

“…Moreover, controlling the dynamic range of the numbers becomes a more severe issue after squaring. In order to eliminate the square, we have proposed to operate on the square root T i (s) = T i (s) of the PEDs [8], which yields an equivalent detector. By taking the square root of (7), we obtain…”

Section: The Square Root Sphere Criterionmentioning

confidence: 99%

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Performance tradeoffs in the VLSI implementation of the sphere decoding algorithm

Burg¹,

Borgmann²,

Simon³

et al. 2004

Fifth IEE International Conference on 3G Mobile Communication Technologies (3G 2004) the Premier Technical Conference for 3G An

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Abstract-Sphere decoding (SD) allows to solve highdimensional MIMO maximum likelihood detection problems with significantly lower complexity than other methods. The SD algorithm has, however, mostly only been analyzed with DSP implementations in mind. We show that VLSI implementations call for new performance metrics, analyze the resulting implementation tradeoffs for the decoding of complex signal constellations, and we develop design guidelines and a generic architecture. When using the ∞ -norm for the sphere constraint instead of the 2 -norm, significant reductions in circuit complexity and improvements in tree pruning efficiency are possible at a minimum performance penalty. As a proof of concept, a high performance ASIC implementation is presented.

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Section: Asic Implementation Resultsmentioning

confidence: 98%

Section: Admissible Intervalsmentioning

confidence: 99%

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Performance tradeoffs in the VLSI implementation of the sphere decoding algorithm

Burg¹,

Borgmann²,

Simon³

et al. 2004

Fifth IEE International Conference on 3G Mobile Communication Technologies (3G 2004) the Premier Technical Conference for 3G An

Self Cite

View full text Add to dashboard Cite

show abstract

“…It can be seen that the proposed hard-output SD implementation without pipelining already outperforms all existing designs without pipelining by a least 23% in terms of area and by at least 28% in terms of clock frequency 6 . Furthermore, the AT-product (in [kGE/MHz]) of the proposed architecture with pipeline interleaving is more than 2× better than that of the pipelined implementation in [27].…”

Section: Implementation Results For Hard-output Sdmentioning

confidence: 97%

“…Nevertheless, symbol-wise pipeline interleaving can be used to shorten the critical path and hence, to improve the AT-product of the SD-core implementation. The main idea of this approach applied to SD is to detect multiple (and independent) symbol-vectors in parallel within the same SD-unit [21,27,28]. Fig.…”

Section: Pipeline Interleavingmentioning

confidence: 99%

VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems

Studer

Wenk

Burg

2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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Abstract. Multiple-input multiple-output (MIMO) technology in combination with orthogonal frequency-division multiplexing (OFDM) is the key to meet the demands for data rate and link reliability of modern wideband wireless communication systems, such as IEEE 802.11n or 3GPP-LTE. The full potential of such systems can, however, only be achieved by high-performance data-detection algorithms, which typically exhibit prohibitive computational complexity. Hard-output sphere decoding (SD) and soft-output single tree-search (STS) SD are promising means for realizing high-performance MIMO detection and have been demonstrated to enable efficient implementations in practical systems. In this chapter, we consider the design and optimization of register transfer-level implementations of hard-output SD and soft-output STS-SD with minimum area-delay product, which are well-suited for wide-band MIMO systems. We explain in detail the design, implementation, and optimization of VLSI architectures and present corresponding implementation results for 130 nm CMOS technology. The reported implementations significantly outperform the area-delay product of previously reported hard-output SD and soft-output STS-SD implementations.

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A Survey of VLSI Implementations of Tree Search Algorithms for MIMO Detection

Bello

Halak

El‐Hajjar

et al. 2015

Circuits Syst Signal Process

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Multiple-input multiple-output (MIMO) detection algorithms have received considerable research interest in recent years, as a result of the increasing need for high data-rate communications. Detection techniques range from the low-complexity linear detectors to the maximum likelihood detector, which scales exponentially with the number of transmit antennas. In between these two extremes are the tree search (TS) algorithms, such as the popular sphere decoder, which have emerged as attractive choices for implementing MIMO detection, due to their excellent performancecomplexity trade-offs. In this paper, we survey some of the state-of-the-art VLSI implementations of TS algorithms and compare their results using various metrics such as the throughput and power consumption. We also present notable contributions that have been made in the last three decades in implementing TS algorithms for MIMO detection, especially with respect to achieving low-complexity, highthroughput designs. Finally, a number of design considerations and trade-offs for implementing MIMO detectors in hardware are presented.

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VLSI implementation of the sphere decoding algorithm

Cited by 31 publications

References 7 publications

Performance tradeoffs in the VLSI implementation of the sphere decoding algorithm

Performance tradeoffs in the VLSI implementation of the sphere decoding algorithm

VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems

A Survey of VLSI Implementations of Tree Search Algorithms for MIMO Detection

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