VLSI programming and silicon compilation-a novel approach from Philips research

Niessen, C.; Berkel, Cady; Rem, Martin; Saeijs, R.W.J.J.

doi:10.1109/iccd.1988.25680

Cited by 30 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In such a case the handshake process may be slowed down, however it will conclude successfully. This argument also applies to easy scalability, since composing asynchronous systems is simply a matter of connecting the proper modules with matching interfacing specifications [21]. This leads to ease of incremental improvement, better technology migration and be able to reuse most of the modules.…”

Section: B the Case For Asynchronous Asics In Metasurfacesmentioning

confidence: 99%

Asynchronous Circuits as an Enabler of Scalable and Programmable Metasurfaces

Petrou

Karousios

Georgiou

2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

Metamaterials and metasurfaces have given possibilities for manipulating electromagnetic (EM) waves that in the past would have seemed impossible. The majority of metasurface designs are suitable for a particular frequency and angle of incidence. One long-sought objective is the design of programmable metasurfaces to dynamically manipulate a variety of incoming EM frequencies and angles. In order to do this, a large-scale mesh of networked chips are required below the metasurface, which apart from adapting electrical impedance properties, also communicate with each other, thus relaying information about meta-atom settings, as well as forwarding possible distributed measurements taken. This paper describes why an asynchronous mixed-signal ASIC is advantageous for the control of scalable, EM absorbing, metasurfaces.

show abstract

Section: B the Case For Asynchronous Asics In Metasurfacesmentioning

confidence: 99%

Asynchronous Circuits as an Enabler of Scalable and Programmable Metasurfaces

Petrou

Karousios

Georgiou

2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…Indeed, there is an important body of work revolving around this idea, for example, [Mar86,Mar87,NvRS88,vS88,OBL98]. Under this light, Geometry of Synthesis (GoS) [Ghi07] can be viewed as a refinement of this early work by using Game Semantics, in lieu of process calculi, as an intermediary for hardware compilation from programming languages to digital circuits.…”

Section: Introduction To Gosmentioning

confidence: 99%

On the Compositionality of Round Abstraction

Ghica

Menaa

2010

CONCUR 2010 - Concurrency Theory

View full text Add to dashboard Cite

Game Semantics is an approach to denotational semantics that has been successful in providing accurate, fully abstract models for various programming languages. It has thereafter been applied, amongst other things, to model checking, access control analysis, information flow analysis, and recently, hardware synthesis.While the roots of modern Game Semantics are sequential, several game models of asynchronous concurrency have since been devised. However, synchronous concurrency has not been considered hitherto.This thesis studies synchronous concurrency in game-like models. The central idea is to investigate deriving such synchronous models from their asynchronous counterparts using round abstraction-a technique that allows aggregating a sequence of computational steps to form a larger, more abstract macro-step.We define round abstraction within a trace-semantic setting that generalises game semantic models. We note that, in general, round abstraction is not compositional. We then identify sufficient conditions to guarantee correct composition, thereby proposing a framework for round abstraction that is sound when applied to synchronous and asynchronous behaviours.

show abstract

Retargeting a hardware compiler using protocol converters

1996

View full text Add to dashboard Cite

We show how to retarget a compiler for occam-like programs from generating two-phase delay-insensitive circuits to generating four-phase speed independent circuits. The specifications of the two-phase circuit elements for our compiler are used to produce a set of equivalent specifications for four-phase circuit elements using a set of protocol converters. Automatic tools have been used in checking that our four-phase implementations satisfy their specifications.

show abstract

VLSI programming and silicon compilation-a novel approach from Philips research

Cited by 30 publications

References 0 publications

Asynchronous Circuits as an Enabler of Scalable and Programmable Metasurfaces

Asynchronous Circuits as an Enabler of Scalable and Programmable Metasurfaces

On the Compositionality of Round Abstraction

Retargeting a hardware compiler using protocol converters

Contact Info

Product

Resources

About