VLSI structures for bit-serial modular multiplication using basis conversion

Abstract

This paper proposes design techniques for the efficient VLSI implementation of bit-serial multiplication over a modulus. These techniques reduce multiplication into simple cyclic shifts, where the number representation of the data is chosen appropriately. This representation will, in general, be highly redundant, implying a relatively poor throughput for the multiplier. It is then shown how, by splitting the multiplier into two pipelined multipliers, the throughput of the unit can be increased, whilst still retaining a cyclic-shift implementation. The split multiplier requires a mid-computation basis conversion, and the two number representations, used within the unit, are only moderately redundant. Thus, highthroughput, bit-serial multipliers are achieved, with most of the complexity contained within systolic basis converter modules. The multipliers are applicable to the VLSI implementation of high-throughput, signal processing operations performed over finite fields, in particular, transform and filter operations. 1 Introduction Recent advances in VLSI technology have suggested novel approaches to the implementation of arithmetic units over algebraic rings and fields other than real or complex [l-41. These new approaches have been spurred on by the need for fault-tolerant, systolic architectures, where throughput is maximised and design complexity minimised. Residue number systems (RNSs) perform arithmetic over a modulus, M where M can be expressed, M = f l ; : ; m i , and all arithmetic can be decomposed into a combination of smaller, parallel, arithmetic subcomputations, thus reducing the granular dimension of any consequent VLSI implementation [S, 61. However, some or all of these mi can still be quite large, hence the need for efficient implementations of modular arithmetic units [2, 4, 7, 81. The concept of basis and basis flow (BF) are defined, and it is shown how, for a specified BF, multiplication by an element q, modm, can be implemented using the exponent, e, as input, where (Be),,, = q, g is an element of the field/ring, and the basis a = g. (+), means the residue 0 IEE, 1994 Paper 1527E (C2, EIO), first &wd 15th July 1993 and in revised form

Unusual-length number-theoretic transforms using recursive extensions of Rader's algorithm

“…In such a case, the NTT of (6) can be computed without multiplication, the multiplications by powers of α being replaced with rotations of x[n] [10,11]. to performing the N p -point NTTs [13]. However, suitable basis converters may not always be feasible and, for word-parallel implementations, a large number of basis converters will be…”

“…It is, therefore, highly suitable for reduced hardware systems. Furthermore, by applying a preliminary basis conversion and matching the basis of the data to the kernel of the small-length NTT [10,11,13], all kernel multiplications can be eliminated, and the only multiplications are the fixed multiplications, inherent in the NTT-based cyclic convolutions, which are required to realise Rader's algorithm. Although this paper develops the theory in terms of the NTT, the extension of Rader's algorithm is equally valid for DFTs, and may be combined with efficient Winograd solutions for small-length DFTs [17] to construct unusual-length DFTs.…”