VLSI technologies for artificial neural networks

Analog Very Large Scale Integration (VLSI) Implementations of Artificial Neural Networks

“…Floating gate transistors can vary charge continuously, thereby the storage cell performs in an analog fashion [26]. The dynamic range for storage devices constructed utilizing floating gate transistors is on the order of 4-6 bits.…”

Mikroelektronische Realisierung von künstlichen neuronalen Netzen/ Microelectronic Realizations of artificial neural networks

“…Offensichtlich müssen Neuro-Chips [6] und VLSI-Bausteine für einen Neurocomputer [10] unterschiedliche Merkmale aufweisen (Bild 3). Da an dieser Stelle nicht der Raum zur Verfügung steht, die für die Realisierung von künstlichen neuronalen Netzen geeigneten Technologien, Formen der Signalverarbeitung, Architektur-und schaltungstechnischen Konzepte in all ihren Ausprägungen [4,5,13,21] zu behandeln, können in diesem Beitrag nur die wichtigsten Punkte angesprochen werden, welche für die zwei Hauptwege des VLSI-Entwurfs von künstlichen neuronalen Netzen zu berücksichtigen sind. Detaillierte Übersichten und Auflistungen von neuronaler Hardware finden sich in [6,11,20].…”

Digital integrated circuit implementations

“…(1988), Sami (1990), Zornetzer et al (1990), Antognetti and Milutinovic (1991), Ramacher and Rückert (1991), Sanchez-Sinencio and Lau (1992), Hassoun (1993), Przytula and Prasama (1993), Delgado-Frias and Moore (1994) and Glesner and Pöchmüller (1994) together with the references therein. Several overview articles or chapters can also be recommended: , Mackie et al (1988), Jackel et al (1987), Jackel (1991), Przytula (1988), DARPA (1989), Del Corso et al (1989), Denker (1986), Goser et al (1989), Personnaz and Dreyfus (1989), Treleaven (1989), Treleaven et al (1989), Schwartz (1990), Burr (1991Burr ( , 1992, Nordström and Svensson (1991), Graf et al (1991Graf et al ( -having many references, 1993, Hirai (1991), Holler (1991), Ienne (1993a, b), Lindsey and Lindblad (1994) and the recent ones-Heemskerk (1995), Hammerstrom (1995) and Morgan (1995). Digital integrated circuit implementations One of the difficult problems when discussing dedicated architectures for artificial neural networks is how to classify them.…”

“…Finally, for neurochips and neurocomputers which are dedicated to a certain neural architecture (e.g., the Boltzmann machine (Murray et al 1992(Murray et al , 1994; Kohonen's self-organizing feature maps (Hochet et al C1.4, C2.1.1 1991, Goser et al 1989, Rüping and Rückert 1996, Tryba et al 1990, Thiran 1993, Thiran et al 1994, Thole et al 1993; Hopfield networks (Blayo and Hurat 1989, Gascuel et al 1992, Graf and de Vegvar C1.3.4 1987a, b, Graf et al 1987, Savran and Morgül 1991, Sivilotti et al 1986, Weinfeld 1989, Yasunaga et al 1989; Neocognitron (Trotin andDarbel 1993, White andElmasry 1992); radial basis functions and C2.1.3, C1.6.2 restricted coulomb energy (LeBouquin 1994, Scofield and Reilly 1991)), or for those which are built as C1.6.3.1 stochastic devices (Clarkson and Ng 1993, Clarkson et al 1993a, b, Köllmann et al 1966, it is almost C1.4 impossible to assess their speed. It should be mentioned that due to such unsurmountable problems there is usually little if any information on benchmarks.…”