VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems

Gojman, Benjamin; DeHon, André

doi:10.1109/fpt.2009.5377684

Cited by 22 publications

(16 citation statements)

References 33 publications

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“…In [29], authors have proposed a mapping algorithm to tolerate variation on threshold voltage of devices at crosspoints. However, this technique assume that at least one k × k (k is determined before fabrication) defect-free crossbar block must exist after fabrication.…”

Section: Previous Workmentioning

confidence: 99%

“…Various types of crossbar defects can be modeled as below: In the proposed weighted tripartite graph model, the delay information for resources within the crossbars is obtained during the characterization testing phase for these devices, in the form of a path delay testing procedure. Since crossbars have a regular structure and they are also reprogrammable, a well-organized delay testing technique can be devised for delay variation characterization [29]. This characterization is done such that the delay variation of nanowires, contact, and crosspoints are lumped into delay variation values for individual crosspoints.…”

Section: Multi-output Nano-crossbar Architecture Modelmentioning

confidence: 99%

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Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures

Ghavami

2016

J Comput Electron

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Nanotechnology-based manufacturing, relying on self-assembly of nanotubes or nanowires, has shown promising potentials for future nanoscale circuit designs. However, high defect density and extreme process variations for crossbar-based nanoarchitectures are expected to be fundamental design challenges. Consequently, defect and variation issues must be considered in logic mapping on nanoscale crossbars. In this paper, we establish a mathematical model for the simultaneous variation and defect-aware logic mapping of multi-outputs crossbar arrays. We model this problem using a new sub-weighted-graph isomorphism problem and propose a greedy algorithm for the variation-and defectaware logic mapping. Based on Monte-Carlo simulation, we compare the proposed technique with other logic mapping techniques such as, variation-unaware and exhaustive search mapping in terms of accuracy as well as runtime. Results show that the effectiveness of our new mapping technique in variation and defect tolerance as well as run time improvement.

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Section: Previous Workmentioning

confidence: 99%

Section: Multi-output Nano-crossbar Architecture Modelmentioning

confidence: 99%

Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures

Ghavami

2016

J Comput Electron

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“…For the bottom-up process, VMATCH [18] is proposed to improve the yield in nano-PLA by improving the timing performance. It identifies the physical gates strength by decreasing order of i ON , through V T measurements, and maps to the high-fanout (logically weak) gates in sequence.…”

Section: Error Detection Correction and Reliabilitymentioning

confidence: 99%

Nanowire FET Circuit Design: An Overview

Chung

2013

Nanowire Field Effect Transistors: Principles and Applications

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Thanks to the short-channel effect suppression of nanowire FET (NWFET), it has become a candidate for the next-generation VLSI device. Different types of NWFETs are introduced to meet the system requirements, with pros and cons. The bottom-up-processed transistor provides the full performance in transistor level, but the integration capability is bounded by the single type of devices per layer and logic design for NMOS and PMOS combined structure is severely restricted. Besides, gate length is relatively large sized, and to overcome this, crossed nanowire transistor-based nanoscale integrated circuit (NASIC) is proposed. Even though this design achieves the minimum area and promises for the large-scale integration so far, the transistor performance is far from the nanotransistor, because of its nonclosed gate structure. Top-down process allows flexible design, but the performance and integration are in its early stage. CMOS interface is required to activate the NW logic and to provide signals from/to conventional system. Abbreviation NWFET

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“…A statistical assembly process results in variations in nanowire geometries and features as they are fabricated individually [8]. Also, statistical alignment during assembly causes variations in field-effect regions as well as random variations from crosspoint to crosspoint in programmable diodes [14]. Due to the low controllability of the manufacturing process, the resistance of defectfree nanowires may vary as well as capacitance [15,16].…”

Section: Introductionmentioning

confidence: 99%

“…The approach in [22] uses a common CMOS based FPGA architecture and enhances it for CNFET. In [14], an algorithm for matching fanouts of the nets to tolerate threshold voltage variation in self-assembled nanoPLAs is presented (logic variation tolerance). On-the-fly mapping for variation tolerance during runtime for crossbar nano architectures has been addressed in [23].…”

Section: Introductionmentioning

confidence: 99%

Variation and defect tolerance for diode-based nano crossbars

Tahoori

2010

Nano Communication Networks

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VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems

Cited by 22 publications

References 33 publications

Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures

Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures

Nanowire FET Circuit Design: An Overview

Variation and defect tolerance for diode-based nano crossbars

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