Voltage Acceleration of TBD and Its Correlation to Post Breakdown Conductivity of N- and P-Channel MOSFETs

Röhner, M.; Kerber, A.; Kerber, M.

doi:10.1109/relphy.2006.251194

Cited by 22 publications

(9 citation statements)

References 18 publications

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“…Long term package level tests confirm that voltage acceleration behaviour of the progressive wear-out is the same as observed for the time to initial formation of the breakdown path itself [10,14].…”

Section: Introductionsupporting

confidence: 60%

“…The same procedure was applied to a second set of devices where a resistor was connected in series to the gate. The proper choice of the resistance value enabled stopping the CVS test after first breakdown [10]. On these samples the CVS test was continued afterwards at a lower stress voltage without a series resistor to study the residual time of progressive wear-out.…”

Section: Methodsmentioning

confidence: 99%

“…With decreasing oxide thickness a progressive characteristic of increasing post-breakdown leakage current has been observed [1], which raised the question about product relevance of gate oxide breakdown criterion. It has been shown that circuits may tolerate breakdowns in the gate oxide [2,3,4,5,6,7] as long as they are soft, which means the conductivity of the breakdown path is low, and this may be the preferred breakdown mode in circuit environments [8,9,10]. If circuits tolerate increased gate leakage currents, the time to exceeding this gate leakage current level becomes the failure criterion of interest rather than the time to initial formation of the breakdown path itself.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Gate voltage and oxide thickness dependence of progressive wear-out of ultra-thin gate oxides

Pompl¹,

Kerber²,

Röhner³

et al. 2006

Microelectronics Reliability

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Section: Introductionsupporting

confidence: 60%

Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Gate voltage and oxide thickness dependence of progressive wear-out of ultra-thin gate oxides

Pompl¹,

Kerber²,

Röhner³

et al. 2006

Microelectronics Reliability

Self Cite

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“…It has been shown that Weibull failure rate distributions (1) provide a good fit for the rate of dielectric breakdown of both pMOS and nMOS transistors [3], [9]. is the probability that failure will occur before time, , and and are the two parameters that characterize the Weibull distribution.…”

Section: Relating Device Failure To Cell Failurementioning

confidence: 99%

Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells

Ahmed

Milor

2012

IEEE Trans. VLSI Syst.

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Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45-nm predictive technology. The DC margins (read, write, and retention) and access times (read and write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a definition for the hard-breakdown point of a cell. An on-chip process, voltage, and temperature tolerant monitoring scheme is proposed to detect the gradual wearout of SRAM cells. The monitoring scheme enables the detection of impending cell failure, which in turn can trigger reconfiguration of the SRAM with redundant rows and/or columns prior to failure.

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“…BD T for NMOS transistors indicates a stronger voltage dependency because of a higher power law exponent, in comparison with PMOS devices [8]. Inserting the power law model in the Weibull distribution function results in:…”

Section: Relating Device Failure To Cell Failurementioning

confidence: 99%

Reliable cache design with detection of gate oxide breakdown using BIST

Ahmed

Milor

2009

2009 IEEE International Conference on Computer Design

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Abstract-Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process after an initial gate leakage increase leading to device failure. It is proposed that if wearout can be monitored, cache arrays with failing cells can be reliably operated after reconfiguration given available memory redundancy.Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45nm predictive technology. The DC margin trends (Read, Write and Retention) and access times (Read and Write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a practical definition for the hardbreakdown point of a cell. Using an on-chip PVT (process, voltage, and temperature) tolerant monitoring scheme, it has been shown that gradual wearout in SRAM cells, due to gate oxide breakdown, is detectible, and cell failure can be predicted before its occurrence.

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Voltage Acceleration of TBD and Its Correlation to Post Breakdown Conductivity of N- and P-Channel MOSFETs

Cited by 22 publications

References 18 publications

Gate voltage and oxide thickness dependence of progressive wear-out of ultra-thin gate oxides

Gate voltage and oxide thickness dependence of progressive wear-out of ultra-thin gate oxides

Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells

Reliable cache design with detection of gate oxide breakdown using BIST

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