Voltage Balancing Control for Series Connected MOSFETs Based on Time Delay Adjustment Under Start-Up and Steady-State Operations

Wãda, Keiji; Shingu, Katsuya

doi:10.1109/ecce.2018.8557461

Cited by 29 publications

(5 citation statements)

References 11 publications

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“…The system is characterized by one switching period delay, which results in a slower response and may lead to initial incorrect error calculation for the PI input. Therefore, it would be beneficial to address the start-up process in terms of software means or auxiliary protective circuits [27].…”

Section: Simulation Studymentioning

confidence: 99%

Active Voltage Balancing of Series-Connected 1.7 kV/325 A SiC MOSFETs Enabling Continuous Operation at Medium Voltage

et al. 2021

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Section: Simulation Studymentioning

confidence: 99%

Active Voltage Balancing of Series-Connected 1.7 kV/325 A SiC MOSFETs Enabling Continuous Operation at Medium Voltage

et al. 2021

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“…Active gate delay compensation techniques tune the gate delay between the serialized devices to achieve voltage balance [30]- [35], which is achieved at a lower complexity compared to active gate control methods, as only the gate delays are adjusted. However, methods implementing active gate delay compensation still require high-bandwidth measurements that are realized with analog-to-digital converters (ADCs) and processed in a digital signal processor (DSP) to calculate the delay time [30]- [34]. A block diagram of a complete closed-loop active gate driving system is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A Hybrid Current- and Voltage-Source Driver for Active Driving of Series-Connected SiC MOSFETs

Ubostad,

Philipps,

Peftitsis

2024

IEEE Trans. Power Electron.

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The series-connection of Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOS-FETs) is an attractive way of increasing the blocking voltage capability of a switch. However, due to inherent transient and steady-state voltage imbalance issues, such a design imposes challenges, especially at elevated switching frequencies, where increased dv/dt is required. This paper proposes a hybrid gate driver for series-connected SiC MOSFETs, which consists of a turn-on stage with a traditional Voltage Source Gate Driver (VSGD), and a turn-off sequence combining a Current Source Gate Driver (CSGD) and a VSGD. The proposed hybrid gate driver can actively control the turn-off dv/dt and di/dt of the switch by adjusting the amplitude of the gate current in the CSGD stage, as well as balance the voltages of the serialized switches by adjusting the timing delays in the driver. This adaptability enables switching loss control of the devices. The proposed driver has been experimentally validated for two seriesconnected SiC MOSFETs. From experiments, it is shown that a voltage imbalance below 2 % can be achieved at direct current (DC)-voltage of 1.5 kV and that switching speeds can be adjusted between 20 kV/µs to 70 kV/µs, while the turn-off switching energy can be reduced by up to 41 %.

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“…This detector is capable of taking the absolute value of an input, comparing it with a threshold value, and outputting 1 if the absolute value of the input exceeds the threshold or 0 if it falls below. Consequently, this paper encompasses the design of both an absolute value module and a comparator module, as well as the implementation of techniques such as introducing delay and reducing supply voltage to minimize detector energy consumption [4]. Utilizing conventional design methodologies, we have analyzed and developed a 4-bit absolute value detector with a delay of 92.4FO4 (1V) and an energy consumption of 53.71Eu (1V).…”

Section: Introductionmentioning

confidence: 99%

A [92.4] FO4(1V), [53.71] Eu(1V) 4-bit absolute-value detector

Huang

2024

ACE

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With the development of modern computers, the integration of chips is getting higher and higher, and as the computing power increases, the energy consumption of chips is also increasing. Therefore, designing and optimizing low-latency and low-energy chips are the goals of many researchers today. At the same time, 4-bit absolute value detector are one of the most basic and important circuits for data storage and processing in chips. This paper designs a 4-bit absolute value detector circuit using Complementary Metal Oxide Semiconductor (CMOS) transistors that can take the absolute value of the input 4-bit signed number and compare it with the threshold value. And it includes the design of its absolute value conversion module and comparator module. By optimizing the circuit structure, the number of logic gates is reduced. By calculating the minimum delay on the critical path, logic gate size and other parameters, the power consumption of the circuit is reduced by adjusting the delay. In conclusion, this paper research can help further optimize the development of chip design industry.

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Voltage Balancing Control for Series Connected MOSFETs Based on Time Delay Adjustment Under Start-Up and Steady-State Operations

Cited by 29 publications

References 11 publications

Active Voltage Balancing of Series-Connected 1.7 kV/325 A SiC MOSFETs Enabling Continuous Operation at Medium Voltage

Active Voltage Balancing of Series-Connected 1.7 kV/325 A SiC MOSFETs Enabling Continuous Operation at Medium Voltage

A Hybrid Current- and Voltage-Source Driver for Active Driving of Series-Connected SiC MOSFETs

A [92.4] FO4(1V), [53.71] Eu(1V) 4-bit absolute-value detector

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