Voltage Island Generation in Cell Based Dual-Vdd Design

Cai, Yici; Liu, Bin; Zhou, Qiang; Hong, Xianlong

doi:10.1093/ietfec/e90-a.1.267

Cited by 6 publications

(5 citation statements)

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“…Guo et al [2] addressed the voltage assignment and voltage island generation problem in placement to minimize the number of level shifters. Cai et al [1] proposed a voltage island generation flow in standard cell-based designs to reduce power consumption under performance constraint and to reduce layout overheads caused by cell clustering to form islands.…”

Section: Introductionmentioning

confidence: 99%

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Multivoltage Floorplan Design

Young

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Energy efficiency has become a very important issue to be addressed in today's system-on-a-chip (SoC) designs. One way to lower power consumption is to reduce the supply voltage. Multisupply voltage (MSV) is thus introduced to provide flexibility in controlling the power and performance tradeoff. In region-based MSV, circuits are partitioned into "voltage islands" where each island occupies a contiguous physical space and operates at one voltage level. These tasks of island partitioning and voltage level assignment should be done simultaneously in the floorplanning process in order to take those important physical information into consideration. In this paper, we consider this core-based voltage island driven floorplanning problem including islands with power down mode, and propose a method to solve it. Given a candidate floorplan solution represented by a normalized Polish expression, we are able to obtain optimal voltage assignment and island partitioning (including islands with power down mode) simultaneously to minimize the total power consumption. Simulated annealing is used as the basic searching engine. By using this approach, we can achieve significant power saving (up to 50%) for all datasets, without any significant increase in area and wire length. We compared our approach with the most updated previous work on the same problem, and results show that our approach is much more efficient and is able to save more power in most cases. We have also studied two other approaches to solve the same problem, a simple dynamic programming approach and a lowest possible power consumption approach. Experimental results show that ours can perform the best among these three approaches. Our floorplanner can also be extended to minimize the number of level shifters, to address a minVdd version of the problem and to simplify the power routing step by placing islands close to their corresponding power pins.

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Section: Introductionmentioning

confidence: 99%

“…Simulated annealing is used with normalized Polish expression (NPE) [10] as the floorplan representation. 1 Our cost function now considers area, wire length, power, and level shifter usage.…”

Section: Introductionmentioning

confidence: 99%

Multivoltage Floorplan Design

Young

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Since two mirrored circuit rows share the same vdd power line, a voltage island must cover two mirrored circuit rows. Also, in order to facilitate the power grid design, the island min-width requirement (Constraint (4) and (5)) is imposed. In this way, both high and low voltage power grid can still use a regular pattern (maybe with different grid pitches).…”

Section: Dual-vdd Island Generationmentioning

confidence: 99%

“…Second, most voltage island works use the region-based approach [4,5,9,11,12,13,14,15,16,19,20,21,22], i.e., partition the design into bins or grids, and all gates within one bin (grid) have the same voltage level. In order to meet the timing requirement, the voltage of one bin/grid is determined by the voltage of the most critical gates in the bin/grid.…”

Section: Introductionmentioning

confidence: 99%

Row based dual-VDD island generation and placement

Xiang

Qian

Zhou

et al. 2014

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

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Power consumption has become a major consideration in nanometer chip design. Since the dynamic power is proportional to V dd 2 , and the static power is proportional to V dd, lowering power supply voltage is an efficient method to reduce the power usage.In this paper, we adopt the row-based dual-supply voltage (DSV) scheme. DSV assigns a low power supply voltage to timing noncritical gates for the power saving. Contrary to the traditional regionbased voltage island works, the row-based approach creates voltage islands along the circuit rows. This kind of fine grid voltage islands give more flexibility on gate voltage assignment such that the low voltage gates can be selected primarily based on timing and design logic, which in turn minimizes the shifter insertion. We present a two-stage flow to generate voltage islands for every two mirrored circuit rows and place gates legally inside each island. To the best of our knowledge, this is also the first work to cover latch and LCB (local clock buffer) handling and shifter placement in voltage island generation. The experimental results demonstrate the effectiveness and efficiency of our approach.

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“…Guo et al [2007] addressed the voltage assignment and voltage island generation problem in placement to minimize the number of level shifters. Cai et al [2007] proposed a voltage island generation flow in standard cell-based designs to reduce power consumption under performance constraints and to reduce layout overheads caused by cell clustering to form islands. In Liu et al [2007] and Lin et al [2010], the voltage assignment problem is solved without any geometrical information.…”

Section: Introductionmentioning

confidence: 99%

Postplacement Voltage Island Generation

Leung

Chio

Young

2012

ACM Trans. Des. Autom. Electron. Syst.

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High power consumption will not only shorten the battery life of handheld devices, but also cause thermal and reliability problems. To lower power consumption, one way is to reduce the supply voltage as in multisupply voltage (MSV) designs. In region-based MSV, a circuit will be partitioned into "voltage islands" where each island occupies a contiguous physical space and operates at one supply voltage. In the work of Wu et al. [2005], this voltage supply problem is addressed, and the input placement is partitioned into a set of rectangular voltage islands by a slicing structure. However, the constraint of using a slicing structure prohibits better solutions in their approach. In the work of Ching et al. [2006], the constraint of obtaining rectangular shapes is relaxed; their method forms islands of very irregular shapes. In this article, we propose a method that focuses on forming rectangular voltage islands to minimize the power consumption, while at the same time favoring the power routing step. It is found that, even with this reduced flexibility on island shapes, we can still perform as well as, or in some cases, even better than the previous work of Ching et al. [2006] that does not control the shapes of the islands, in terms of power saving and island number.

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Voltage Island Generation in Cell Based Dual-Vdd Design

Cited by 6 publications

References 0 publications

Multivoltage Floorplan Design

Multivoltage Floorplan Design

Row based dual-VDD island generation and placement

Postplacement Voltage Island Generation

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