Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs

Jang, Cheoljon; Chong, Jong‐Wha

doi:10.4218/etrij.14.0113.1233

Cited by 3 publications

(2 citation statements)

References 23 publications

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“…To summarise, the problem can be specified as follows: To minimise power routing area A routing and the number of power bumps/TSVs N bump/TSV . Independent variables: M i , w i ( i represents the i th die in 3D IC). Constraints: IR‐drop < 5% VDD. The widths of power wires should be limited to the minimum width allowed, that is

w_{i} \geq w_{i, min}

The power routing area A routing should not cover too much metal resources [27]

% cov = \frac{A_{routing}}{A_{chip}} \leq % {cov}_{max}

…”

Section: Problem Formulationmentioning

confidence: 99%

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Concurrent optimisation method for three‐dimensional power delivery network design

Xie

Tian

Wang

2016

IET Circuits, Devices & Systems

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Power distribution network (PDN) design in three-dimensional integrated circuit (3D IC) is one of the most important challenges. Power wires and power bumps or power through-silicon-vias (TSVs) are the two major factors that affect the voltage as the IR-drop of 3D ICs. Different parameters of power wires and different insertions of power bumps/TSVs cause different IR-drop distribution. In this study, the authors propose 3D power concurrent optimisation to achieve a multi-objective design for 3D IC PDN, which optimises the insertion of power bumps/TSVs according to the IR-drop distribution and concurrently reduces the power wire's routing area so as to lower the metal coverage rate, guaranteeing the IR-drop and other constraints. Results of the experiments show that the proposed method can get more solutions than one after a run with both less power routing area and less number of power bumps/TSVs. In addition, the experiments also show that it is more effective and efficient than the classical exhaustive method.

show abstract

w_{i} \geq w_{i, min}

The power routing area A routing should not cover too much metal resources [27]

% cov = \frac{A_{routing}}{A_{chip}} \leq % {cov}_{max}

…”

Section: Problem Formulationmentioning

confidence: 99%

“…The power routing area A routing should not cover too much metal resources [27]

% cov = \frac{A_{routing}}{A_{chip}} \leq % {cov}_{max}

…”

Section: Problem Formulationmentioning

confidence: 99%

Concurrent optimisation method for three‐dimensional power delivery network design

Xie

Tian

Wang

2016

IET Circuits, Devices & Systems

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Electrical modeling of carbon nanotube‐based shielded through‐silicon vias for three‐dimensional integrated circuits

Zhao

et al. 2020

Int J Numerical Modelling

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In this article, two kinds of shielded carbon nanotube (CNT) through-silicon vias (TSV) are proposed and investigated for high-density three-dimensional integrated circuits (3-D ICs). First, vertical aligned CNT array is inserted into a single hole, and two isolated metal pads, that is, the central circular and outer annular pads, are deposited onto the surface to make distinct conduction paths. The shielded CNT TSV, which can also be named as coaxial TSV, is formed, with the semiconducting CNTs utilized to suppress lateral conductance. Based on a similar concept, the shielded differential CNT TSV is developed. By virtue of the proposed shielded CNT TSVs, the chip area can be saved significantly. The equivalent circuit models are established for the proposed shielded CNT TSVs. A passive equalizer is designed to improve the signal quality for shielded differential CNT TSV. Finally, the potential applications of the proposed TSVs in 3-D IC power distribution network design are investigated.

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Power noise isolation in a silicon interposer with through silicon vias

Kim

Shin

et al. 2014

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)

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Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs

Cited by 3 publications

References 23 publications

Concurrent optimisation method for three‐dimensional power delivery network design

Concurrent optimisation method for three‐dimensional power delivery network design

Electrical modeling of carbon nanotube‐based shielded through‐silicon vias for three‐dimensional integrated circuits

Power noise isolation in a silicon interposer with through silicon vias

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