Voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in organic inverter configuration

Kim, Min‐Hoi; Lee, Gyu Jeong; Keum, Chang‐Min; Lee, Sin‐Doo

doi:10.1016/j.orgel.2013.02.023

Cited by 5 publications

(9 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The basic fabrication process for the FeOFETs followed that of previous reports. 12,20) Glass substrates were cleaned sequentially with acetone, isopropyl alcohol, methyl alcohol, and deionized water in an ultrasonicater for 10 min each. For the gate electrode, 50-nm-thick aluminum was thermally deposited on the glass substrate through a shadow mask.…”

Section: Experimental Methodsmentioning

confidence: 99%

“…For the off-(erased) state, a large positive gate voltage (60 V) was applied, and the source and drain electrodes were grounded. 20) In this study, the memory-off state was measured initially, and the memory-on state was measured subsequently. In this regard, there was not any electrical difference, even if the off-and on-current measurement order was inverted.…”

Section: Memory Properties Of the Scc-processed Feofetmentioning

confidence: 99%

“…As the drain current in the off-state was primarily determined by the turn-on voltage and gate leakage current, the I OFF of the 10-FeOFET did not show a large increase. 12,20) Reducing the reading voltage is one of the important steps in avoiding the degradation of dipolar states and large power consumption. 2) Figure 5(c) shows the memory on-and offcurrents of the 10-FeOFET when a very low drain voltage (−1 V) was applied.…”

Section: Memory Properties Of the Scc-processed Feofetmentioning

confidence: 99%

See 2 more Smart Citations

Surface engineering of ferroelectric polymer for the enhanced electrical performance of organic transistor memory

Kim

Lee

et al. 2018

Jpn. J. Appl. Phys.

Self Cite

View full text Add to dashboard Cite

We suggest a viable surface control method to improve the electrical properties of organic nonvolatile memory transistors. For viable surface control, the surface of the ferroelectric insulator in the memory field-effect transistors was modified using a smooth-contact-curing process. For the modification of the ferroelectric polymer, during the curing of the ferroelectric insulators, the smooth surface of a soft elastomer contacts intimately with the ferroelectric surface. This smooth-contact-curing process reduced the surface roughness of the ferroelectric insulator without degrading its ferroelectric properties. The reduced roughness of the ferroelectric insulator increases the mobility of the organic field-effect transistor by approximately eight times, which results in a high memory on-off ratio and a low-voltage reading operation.

show abstract

Section: Experimental Methodsmentioning

confidence: 99%

Section: Memory Properties Of the Scc-processed Feofetmentioning

confidence: 99%

Section: Memory Properties Of the Scc-processed Feofetmentioning

confidence: 99%

See 1 more Smart Citation

Surface engineering of ferroelectric polymer for the enhanced electrical performance of organic transistor memory

Kim

Lee

et al. 2018

Jpn. J. Appl. Phys.

Self Cite

View full text Add to dashboard Cite

show abstract

“…The thickness of the P(VDF-TrFE) film was measured to be 630 nm. For the interconnection of the memory transistor and the selection transistor, a via hole was produced using a solvent-drop method [3,6]. In fabricating a selection transistor, a fluorinated polymer (NovecTM EGC-1700, 3M) was chosen as the PDL which was patterned on the ferroelectric insulator by transferprinting [6,7].…”

Section: Methodsmentioning

confidence: 99%

“…For a single cell, the rewritability of the ferroelectric memory is typically achieved using the polarization direction of the ferroelectric insulator [1,2,6]. However, this approach will not be applicable for an array with multiple cells because of the crosstalk among the cells in the same row or column.…”

Section: Introductionmentioning

confidence: 99%

Concept of rewritable organic ferroelectric random access memory in two lateral transistors-in-one cell architecture

Kim¹,

Lee²,

Keum³

et al. 2014

Semicond. Sci. Technol.

Self Cite

View full text Add to dashboard Cite

We propose a concept of rewritable ferroelectric random access memory (RAM) with two lateral organic transistors-in-one cell architecture. Lateral integration of a paraelectric organic field-effect transistor (OFET), being a selection transistor, and a ferroelectric OFET as a memory transistor is realized using a paraelectric depolarizing layer (PDL) which is patterned on a ferroelectric insulator by transfer-printing. For the selection transistor, the key roles of the PDL are to reduce the dipolar strength and the surface roughness of the gate insulator, leading to the low memory on-off ratio and the high switching on-off current ratio. A new driving scheme preventing the crosstalk between adjacent memory cells is also demonstrated for the rewritable operation of the ferroelectric RAM.

show abstract

Solution‐Processed Dual Gate Ferroelectric–Ferroelectric Organic Polymer Field‐Effect Transistor for the Multibit Nonvolatile Memory

Boampong

Cho

Choi

et al. 2021

Adv Elect Materials

View full text Add to dashboard Cite

The stable multibit storage operation of solution‐processed organic nonvolatile memories (ONVMs) based on ferroelectric field‐effect transistors (FeFETs) for high density data storage devices are demonstrated. The proposed multibit ONVM structure consists of a p‐type polymer semiconductor sandwiched between poly(vinylidene fluoride‐trifluoroethylene) [P(VDF‐TrFE)] layers serving as ferroelectric gate insulators to form a dual gate ferroelectric–ferroelectric memory transistor (DG Fe‐FeMT). With the extra memory space created by the spatially separated ferroelectrics, a 2‐bit memory representation (“11”, “10”, “01” and “00”) with clear memory margins is achieved due to the bistability of each P(VDF‐TrFE) and the high performance of the polymer semiconductor. The distinct four‐level reading of memory output currents (IM,OUTs) results from the independent programming voltages of the dual gates. An excellent distinct six‐level IM,OUTs are also achieved in DG Fe‐FeMT using the intermediate programming voltages. Finally, the possibility of 3−bit, or 8 memory states, are demonstrated by optimizing the bistability and intermediate polarization states of the ferroelectrics without increasing the device area horizontally. The DG Fe‐FeMT has a great potential for cost−effective flexible nonvolatile multibit data storage devices due to its solution‐process and low annealing temperatures.

show abstract

Voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in organic inverter configuration

Cited by 5 publications

References 11 publications

Surface engineering of ferroelectric polymer for the enhanced electrical performance of organic transistor memory

Surface engineering of ferroelectric polymer for the enhanced electrical performance of organic transistor memory

Concept of rewritable organic ferroelectric random access memory in two lateral transistors-in-one cell architecture

Solution‐Processed Dual Gate Ferroelectric–Ferroelectric Organic Polymer Field‐Effect Transistor for the Multibit Nonvolatile Memory

Contact Info

Product

Resources

About