Materials Science in Semiconductor Processing
 2021
DOI: 10.1016/j.mssp.2020.105612
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Voltage stress induced interface states and hole trapping in germanium pMOSFETs with high-k gate dielectric and metal-gate electrode

Fu-Chien Chiu
1
,
Wei-Chia Chen
2
,
Jih‐Huah Wu
3
et al.
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