Voltage-tolerant circuit design for fully CMOS-compatible differential multiple-time programmable nonvolatile memories

Abstract

In this paper, a fully CMOS-compatible differential multiple-time programmable (DFMTP) nonvolatile memory (NVM) circuit, fabricated by the standard TSMC 0.18 µm CMOS process without violating the design and electrical rules, is proposed. Novel voltage-tolerant circuits were designed using the standard 3.3 and 1.8 V devices for the bit line (BL) and control gate (CG) drivers for −3 and 6 V program/erase operations, as well as the negative voltage isolation circuits for sense amplifiers. The DFMTP array with these voltage-tolerant control circuits was used and measured to confirm the correct program/erase/read operations.