Vth-tunable CMIS platform with high-k gate dielectrics and variability effect for 45nm node

Hayashi, Takashi; Mizutani, Masaharu; Inoue, Masashi; Yugami, J.; Tsuchimoto, J.; Anma, Masatoshi; Komori, S.; Tsukamoto, K.; Tsukamoto, Yasumasa; Nii, Koji; Nishida, Y.; Sayama, H.; Yamashita, T.; Oda, H.; Eimori, T.; Ohji, Yuzuru

doi:10.1109/iedm.2005.1609505

Cited by 7 publications

(1 citation statement)

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“…EOT reduction raises the MOSFET drain current (I D ) or lowers the supply voltage (V DD ), thereby maintaining an acceptable drain current. In addition, EOT reduction is required to suppress the short channel effect and minimize the variety of threshold voltages (V th ) (1). In order to meet these requirements of CMOS scaling, intensive efforts to make SiON gate dielectrics more nitrogen rich have been made (2)(3)(4)(5).…”

Section: Introductionmentioning

confidence: 99%

The Impact of F and N Incorporation Technique on Advanced Gate Stacks

et al. 2007

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Control of threshold voltage (Vth) is a common and serious problem for realizing scalable LSIs with either nitrogen rich SiON, high-k gate dielectrics, or metal gates. In this paper, we demonstrate the improvement of HfSiON pMISFETs characteristics with the F incorporation technique, which may prove to be a powerful tool for lowering |Vth| in pMISFET with both poly-Si and metal gates. Using F implantation in the channel region prior to HfSiON formation, |Vth| lowering up to ~200mV is obtained without mobility degradation. In the same manner as the F incorporation technique, N incorporation is useful for reducing Vth value in nMISFETs. Furthermore, the impact of F incorporation in HfSiON is investigated in terms of reliability. From a comparison of the F incorporation effect on SiON and HfSiON gate dielectrics, we have proposed a model for the F passivation of defects in both HfSiON and the HfSiON/Si interface.

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