Vulnerability Analysis for Custom Instructions

Abstract

Today circuits are becoming more vulnerable to electronic noises and reliable system design has emerged as a key challenge to embedded system design. Logic fault in terms of soft errors or transient faults are now a serious problem for embedded processors. Recent developments in customized embedded processors significantly focus on improving the performance and area of the processor by augmenting it with application specific custom functional units that implement custom instructions. This paper analyzes the effect of type, order, and bit-width of the operations of different custom instruction sub-graphs on the vulnerability of extensible processors. We have developed a framework for studying the effects of different operations and their dependencies on overall vulnerability of the custom functional units and our experiments show that, in most cases, similar custom functional units could have different vulnerabilities to soft errors. Our approach enables designers to optionally constrain the operand types and also the custom functional unit structure to reach an acceptable vulnerability.

Fault tolerant task scheduling algorithm for multicore systems

“…The execution time of the tasks are obtained from the real value of six types of benchmark tasks (Fibonacci sequence, Bubble Sorting, Factorial Function, Multiplying Matrix Function, Newton Root and Sum of Squares) and AVF of these tasks are calculated by the method in [18] [19][20] [21]. The results are obtained by taking average of 10 times repetition.…”

Cross-layer custom instruction selection to address PVTA variations and soft error

“…As outlined by the International Technology Roadmap for Semiconductors (ITRS) [10], vulnerability to soft errors has raised as one of the major reliability metrics of modern VLSI chips including embedded processors [31,32]. When a high-energy particle hits a sensitive region of a CI, a transient glitch is generated.…”